EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 592
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
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Manufacturer
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- EP2AGX45CU17C6N PDF datasheet
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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4–18
Figure 4–12. Reset Sequence in Basic ×1 Mode with Receiver CDR in Automatic Lock Mode (Channel and TX PLL
select/reconfig Option)
Arria II Device Handbook Volume 2: Transceivers
Reset Sequence with the Channel and TX PLL Select/Reconfig Option
Reset and Control Signals
Output Status Signals
Use the example reset sequence shown in
dynamic reconfiguration controller to change the TX PLL settings of the transceiver
channel. In this example, the dynamic reconfiguration is used to dynamically
reconfigure the data rate of the transceiver channel configured in Basic ×1 mode with
the receiver CDR in automatic lock mode.
As shown in
dynamic reconfiguration controller to change the configuration of the transceiver
channel:
1. After power up and establishing that the transceiver is operating correctly, write
2. Assert the tx_digitalreset, rx_analogreset, and rx_digitalreset signals.
3. As soon as write_all is asserted, the dynamic reconfiguration controller starts to
4. Wait for the assertion of the channel_reconfig_done signal (marker 4), which
reconfig_mode_sel[2:0]
channel_reconfig_done
the new value in the appropriate registers (including reconfig_mode_sel[2:0])
and subsequently assert the write_all signal (marker 1) to initiate the dynamic
reconfiguration.
f
execute its operation, as indicated by the assertion of the busy signal (marker 2).
indicates the completion of dynamic reconfiguration in this mode.
rx_analogreset
rx_digitalreset
tx_digitalreset
rx_reqlocked
For more information, refer to
Reconfiguration in Arria II
write_all
Figure
busy
4–12, perform the following reset procedure when using the
New Value
1
1
1
2
Devices.
3
Chapter 4: Reset Control and Power Down in Arria II Devices
AN 558: Implementing Dynamic
4
Figure 4–12
five parallel clock cycles
5
6
7
4 μs
8
when you are using the
Dynamic Reconfiguration Reset Sequences
December 2010 Altera Corporation
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