EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 260
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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8–20
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Differential I/O Termination
f
The Arria II device family provides a 100-Ω R
receiver channel for LVDS standards. OCT saves board space by eliminating the need
to add external resistors on the board. You can enable OCT in the Quartus II software
Assignment Editor.
For Arria II GX devices, OCT is supported in the top, right, and bottom I/O banks.
Arria II GX clock input pins (CLK[4..15]) do not support OCT. For Arria II GZ
devices, R
(CLK[0,2,9,11]). It is not supported for column I/O pins and dedicated clock input
pins (CLK[1,3,8,10]).
Figure 8–16
Figure 8–16. LVDS Input Buffer I/O R
Table 8–7
Quartus II software Assignment Editor.
Table 8–7. Differential Input OCT in Quartus II Software Assignment Editor
For more information, refer to
Input Termination (Accepts wildcards/groups)
lists the assignment name and its value for differential input OCT in the
D
OCT is supported on all row I/O pins and dedicated clock input pins
shows LVDS input OCT.
Assignment Name
Transmitter
LVDS
Chapter 8: High-Speed Differential I/O Interfaces and DPA in Arria II Devices
I/O Features in Arria II Devices
D
OCT
Z
Z
0
0
= 50 Ω
= 50 Ω
D
OCT option on each differential
Arria II Differential
R
Receiver with
D
R
= 100 Ω OCT
D
December 2010 Altera Corporation
chapter.
Assignment Value
Differential
Differential Receiver
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