EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 398

• Manufacturer Part Number: EP2AGX95EF29I5N
• Description: IC ARRIA II GX FPGA 95K 780FBGA
• Manufacturer: Altera
• Series: Arria II GXr

Specifications of EP2AGX95EF29I5N

• Number Of Logic Elements/cells: 89178
• Number Of Labs/clbs: 3747
• Total Ram Bits: 6679
• Number Of I /o: 372
• Voltage - Supply: 0.87 V ~ 0.93 V
• Mounting Type: Surface Mount
• Operating Temperature: -40°C ~ 100°C
• Package / Case: 780-FBGA
• Family Name: Arria® II GX
• Number Of Logic Blocks/elements: 93674
• # I/os (max): 372
• Frequency (max): 500MHz
• Operating Supply Voltage (typ): 900mV
• Logic Cells: 93674
• Ram Bits: 7025459.2
• Operating Supply Voltage (min): 0.87V
• Operating Supply Voltage (max): 0.93V
• Operating Temp Range: -40C to 100C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 780
• Package Type: FC-FBGA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Number Of Gates: -
• Lead Free Status / Rohs Status: Compliant

1–12
Transmitter Channel Datapath
Figure 1–11. Transmitter Channel Datapath
Table 1–4. Transmitter Phase Compensation FIFO Modes for Arria II Devices
Arria II Device Handbook Volume 2: Transceivers
Low Latency
High Latency
Register
Notes to
(1) Automatically set when you select a protocol in the ALTGX MegaWizard Plug-In Manager.
(2) Pending characterization.
Fabric
FPGA
Table
Transmitter PCS
Mode
hard IP
PCIe
1–4:
f
This section describes the Arria II GX and GZ transmitter channel datapath
architecture. The sub-blocks in the transmitter datapath are described in order from
the TX phase compensation FIFO buffer at the FPGA fabric-to-transceiver interface to
the transmitter input buffer.
Figure 1–11
This section describes the transmitter PCS modules, which consists of the TX phase
compensation FIFO, byte serializer, and 8B/10B encoder.
The tx_digitalreset signal resets all modules in the transmitter PCS block.
For more information about the tx_digitalreset signal, refer to the
Power Down in Arria II Devices
TX Phase Compensation FIFO
This FIFO compensates for the phase difference between the low-speed parallel clock
and the FPGA fabric interface clock.
phase compensation FIFO.
4-words deep
8-words deep
Interface
FIFO Depth
PIPE
—
shows the transmitter channel datapath.
Compensation
2-to-3 parallel clock cycles
4-to-5 parallel clock cycles
TX Phase
FIFO
Latency Through FIFO
chapter.
1
Transmitter Channel PCS
Byte Serializer
Table 1–4
(2)
(2)
Chapter 1: Transceiver Architecture in Arria II Devices
lists the available modes for the TX
All functional modes except PCIe and
Applicable Functional Modes
8B/10 Encoder
Deterministic Latency
Deterministic Latency
December 2010 Altera Corporation
Transmitter Channel Datapath
PCIe
Transmitter Channel PMA
Reset Control and
Serializer
(1)