EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 530
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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2–40
Arria II Device Handbook Volume 2: Transceivers
Table 2–11
editor.
Table 2–11. Quartus II Assignments for Arria II Devices
From
To
Assignment Name
Value
Note to
(1) You can find the full hierarchy name of the 0 PPM clock driver using the Node Finder feature in the Quartus II
Assignment Editor.
Assignment
Table
lists the Quartus II assignments that you must make in the assignment
2–11:
Full design hierarchy name of one of the following clock drivers that you
choose to drive the tx_coreclk ports of all identical channels (1):
■
■
■
■
■
tx_dataout pins of all identical channels whose tx_coreclk ports are
connected together and driven by the 0 PPM clock driver.
GXB 0 PPM Core Clock Setting
ON
tx_clkout
coreclkout
FPGA CLK input pins
Transceiver REFCLK pins
Clock output from left corner PLLs
Chapter 2: Transceiver Clocking in Arria II Devices
Description
FPGA Fabric-Transceiver Interface Clocking
December 2010 Altera Corporation
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