EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 27
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
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- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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Chapter 1: Overview for the Arria II Device Family
Arria II Device Architecture
December 2010 Altera Corporation
SEU Mitigation
JTAG Boundary Scan Testing
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Remote System Upgrade
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Offers built-in error detection circuitry to detect data corruption due to soft errors
in the configuration random access memory (CRAM) cells
Allows all CRAM contents to be read and verified to match a
configuration-computed cyclic redundancy check (CRC) value
You can identify and read out the bit location and the type of soft error through the
JTAG or the core interface
Supports JTAG IEEE Std. 1149.1 and IEEE Std. 1149.6 specifications
IEEE Std. 1149.6 supports high-speed serial interface (HSSI) transceivers and
performs boundary scan on alternating current (AC)-coupled transceiver channels
Boundary-scan test (BST) architecture offers the capability to test pin connections
without using physical test probes and capture functional data while a device is
operating normally
Allows error-free deployment of system upgrades from a remote location
securely and reliably without an external controller
Soft logic (either the Nios II embedded processor or user logic) implementation
in the device helps download a new configuration image from a remote
location, store it in configuration memory, and direct the dedicated remote
system upgrade circuitry to start a reconfiguration cycle
Dedicated circuitry in the remote system upgrade helps to avoid system down
time by performing error detection during and after the configuration process,
recover from an error condition by reverting back to a safe configuration
image, and provides error status information
Arria II Device Handbook Volume 1: Device Interfaces and Integration
1–13
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