EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 513
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EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
- EP2AGX45CU17C6N PDF datasheet
- EP2AGX45CU17C6N PDF datasheet #2
- EP2AGX45CU17C6N PDF datasheet #3
- EP2AGX45CU17C6N PDF datasheet #4
- EP2AGX45CU17C6N PDF datasheet #5
- EP2AGX95EF29I5N PDF datasheet #6
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- Download datasheet (22Mb)
Chapter 2: Transceiver Clocking in Arria II Devices
Transceiver Channel Datapath Clocking
Figure 2–15. Receiver Datapath Clocking in ×4 Bonded Channel Configuration with Deskew FIFO
December 2010 Altera Corporation
Fabric
FPGA
hard IP
hard IP
hard IP
hard IP
PCIe
PCIe
PCIe
PCIe
coreclkout
×4 Bonded Channel Configuration with Deskew FIFO
XAUI functional mode has ×4 bonded channel configuration with deskew FIFO.
Figure 2–15
with deskew FIFO.
Interface
Interface
Interface
Interface
PIPE
PIPE
PIPE
PIPE
Channel 3
Channel 2
Channel 1
Channel 0
shows receiver datapath clocking in ×4 channel bonding configurations
Input Reference Clock
Input Reference Clock
/2
/2
/2
/2
/2
CMU1_PLL
CMU0_PLL
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
Receiver Channel PCS
CMU1 Clock Divider
CMU0 Clock Divider
Arria II Device Handbook Volume 2: Transceivers
CMU1_Channel
CMU0_Channel
Ch3
Ch2
Ch1
Low-Speed Parallel Clock from CMU0 Clock Divider
FPGA Fabric-Transceiver Interface Clock
Serial Recovered Clock
Ch0 Parallel Recovered Clock
Receiver Channel
Receiver Channel
Receiver Channel
Receiver Channel
PMA
PMA
PMA
PMA
Reference
Reference
Reference
Reference
Clock
Clock
Clock
Clock
Input
Input
Input
Input
2–23
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