EP2AGX95EF29I5N Altera, EP2AGX95EF29I5N Datasheet - Page 132
EP2AGX95EF29I5N
Manufacturer Part Number
EP2AGX95EF29I5N
Description
IC ARRIA II GX FPGA 95K 780FBGA
Manufacturer
Altera
Series
Arria II GXr
Datasheets
1.EP2AGX45CU17C6N.pdf
(96 pages)
2.EP2AGX45CU17C6N.pdf
(14 pages)
3.EP2AGX45CU17C6N.pdf
(692 pages)
4.EP2AGX45CU17C6N.pdf
(10 pages)
5.EP2AGX45CU17C6N.pdf
(88 pages)
6.EP2AGX95EF29I5N.pdf
(306 pages)
Specifications of EP2AGX95EF29I5N
Number Of Logic Elements/cells
89178
Number Of Labs/clbs
3747
Total Ram Bits
6679
Number Of I /o
372
Voltage - Supply
0.87 V ~ 0.93 V
Mounting Type
Surface Mount
Operating Temperature
-40°C ~ 100°C
Package / Case
780-FBGA
Family Name
Arria® II GX
Number Of Logic Blocks/elements
93674
# I/os (max)
372
Frequency (max)
500MHz
Operating Supply Voltage (typ)
900mV
Logic Cells
93674
Ram Bits
7025459.2
Operating Supply Voltage (min)
0.87V
Operating Supply Voltage (max)
0.93V
Operating Temp Range
-40C to 100C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
780
Package Type
FC-FBGA
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Number Of Gates
-
Lead Free Status / Rohs Status
Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
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5–28
Arria II Device Handbook Volume 1: Device Interfaces and Integration
Source-Synchronous Mode for LVDS Compensation
The goal of source-synchronous mode for LVDS compensation is to maintain the same
data and clock timing relationship seen at the pins at the internal
serializer/deserializer (SERDES) capture register, except that the clock is inverted
(180° phase shift), as shown in
the delay of the LVDS clock network plus any difference in the delay between these
two paths:
■
■
Figure 5–21. Source-Synchronous Mode for LVDS Compensation for Arria II Devices
No-Compensation Mode
In no-compensation mode, the PLL does not compensate for the clock networks. This
mode provides better jitter performance because the clock feedback into the PFD
passes through less circuitry. Both the PLL internal and external clock outputs are
phase-shifted with respect to the PLL clock input.
waveform of the PLL clocks’ phase relationship in no-compensation mode.
Data pin-to-SERDES capture register
Clock input pin-to-SERDES capture register. In addition, the output counter must
provide the 180° phase shift.
Clock at register
Data at register
reference clock
at input pin
Data pin
PLL
Figure
5–21. Thus, this mode ideally compensates for
Chapter 5: Clock Networks and PLLs in Arria II Devices
Figure 5–22
December 2010 Altera Corporation
shows an example
PLLs in Arria II Devices
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