pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 108

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pc87591l

Manufacturer Part Number
pc87591l
Description
Lpc Mobile Embedded Controllers
Manufacturer
National Semiconductor Corporation
Datasheet

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Embedded Controller Modules
Pending Flags
An occurrence of a trigger condition for the Multi-Input Wake-Up input is latched into the respective pending bit in WKPNDx
register. The respective bits of WKPNDx are set on an occurrence of the selected trigger edge on the corresponding input
signal.
Since the WKPNDx register holds a pending wake-up condition until it is cleared, the device does not enter the IDLE mode
if any wake-up bit is both enabled and pending. Consequently, the pending flags must be cleared before an attempt to enter
the Idle mode.
Input Enable
The MIWU utilizes multiple Multi-input Wake-Up signals. Setting the appropriate bits in the WKENAx registers select which
particular wake-up signal causes the device to exit Idle mode.
Interrupts
The combined output of all pending and enabled channels of the MIWU module generates the wake-up signal, which is fed
into both the Power Management Control module (PMC) and the Interrupt Control Unit (ICU). Therefore, each wake-up of
the device can be followed by a wake-up interrupt. Since the device can not enter the power reduction mode without having
the core execute a “WAIT” instruction, a wake-up interrupt is needed to terminate the “WAIT” instruction on wake-up.
MIWU outputs WKO10 through WKO37 may be connected to the Interrupt Control Unit (ICU) to generate an interrupt asso-
ciated with the specific MIWU output. The WKOxx behaves as follows:
Note: To enable and disable ICU interrupts generated by their associated WKOxx output of the MIWU, use the ICU mask
register in the ICU.
In addition, the MIWU provides four interrupt request lines: WKINTA, WKINTB, WKINTC and WKINTD (see Figure 32 on
page 107). These are routed to the ICU (except WKINTB) and can request an interrupt if a valid trigger condition occurred
on any of the enabled input sources within the group of eight inputs associated with the interrupt line. For a detailed summary
of the interrupts available, see Table 17 on page 105.
When the respective WKENxx bit is cleared, the WUIxx is connected to the ICU directly (bypassing the edge detec-
tors and pending bits). The ICU can be configured to use the signal as a level or edge triggered interrupt.
When the respective WKENxx bit is enabled, the output of the pending bit, WKPDxx, is connected to WKOxx.
(Continued)
108
Revision 1.07

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