pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 351

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
6.0 Host-Controlled Modules and Host Interface
Shared Memory Configuration Register
This register is reset on host domain hardware reset to 00
Location: Index F4
Type: R/W
Shared Memory Base Address High Byte Register
This register describes the high byte for the user-defined memory zone mapped to the shared memory (decoded as bits 31
to 24 of the 32-bit address range, bits 15-0 are 0). This register is reset to 00
Location: Index F5
Type: R/W
Bit
Name
Reset
Bit
Name
Reset
7-4
Bit
7-0
Bit
0
1
2
3
BIOS LPC Enable. Enables the PC87591x to respond to LPC memory accesses to the BIOS-LPC space. The
reset value of this register is defined by the SHBM configuration inputs. The value of this bit is updated later,
based on the detected host BIOS scheme; see “Memory Range Programing” on page 350 for details.
0: Disabled (default when SHBM disable BIOS configuration)
1: Enabled (default when SHBM enable BIOS configuration)
BIOS Extended Space Enable. Expands the BIOS address space to which the PC87591x responds to include
the Extended BIOS address range.
0: Disabled (default)
1: Enabled
User-Defined Memory Space Enable. When set, enables the PC87591x to respond to LPC memory read and
write accesses in the user-defined memory area range. The base address and size of the user-defined range
are specified by the Shared Memory Base Address High and Low Byte registers and the Shared Memory Size
Configuration register.
0: Disabled (default)
1: Enabled
BIOS FWH Enable. When set, enables PC87591x response to LPC-FWH transactions to the BIOS-FWH
space. The reset value of this register is defined by the XCNF(2-0) configuration inputs. The value of this bit is
later updated based on the detected host BIOS scheme; see “Memory Range Programing” on page 350 for
details.
0: Disabled (default when SHBM disable BIOS configuration)
1: Enabled (default when SHBM enable BIOS configuration)
BIOS FWH ID. These four bits correspond to the identification nibble, which is part of a FWH transaction (see
Section 6.1.7 for details).
User-Defined Memory Zone Address High. Defines the higher eight bits of the user-defined memory block
base address. The base address should be aligned on the selected block size.
16
16
7
0
7
0
6
0
6
0
BIOS FWH ID
User-Defined Memory Zone Address High
5
0
5
0
16
Description
Description
351
or 09
4
0
4
0
16
, depending on the value of the SHBM strap input.
BIOS FWH
(Continued)
Enable
Strap
3
3
0
16
on Host Domain Hardware reset.
Memory
Defined
Enable
Space
User-
2
0
2
0
Extended
Enable
Space
BIOS
1
0
1
0
BIOS LPC
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Enable
Strap
0
0
0