pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 79

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
4.0 Embedded Controller Modules
4.1.7
When FRE bit in SZCFGn register is 1, the fast read bus cycle is enabled for zone n. The fast read bus cycle takes one clock
cycle.
At the start of the T1-2 clock cycle, the address is placed on the address bus, and SELn and RD are activated. WR0-1 are
inactive, indicating a read bus cycle. At the end of the clock cycle, the BIU samples the data. SELn and RD are deactivated
in the following clock cycle, unless another read from the same zone follows. If a write to the same zone follows and late
write is configured, SELn remains activated. The address remains valid until the start of the clock cycle after the T1-2 clock
cycle.
Fast Read Bus Cycle
Bus State
Bus State
CLK
A0-19
SELn
D0-7
RD
WR0-1
BST0-2
CLK
A0-19
SELn
D0-7
RD
WR0-1
BST0-2
Figure 22. Normal Read Bus Cycle with 2 Internal Waits and 1 Wait on Burst
Figure 21. Normal Read Bus Cycle with 0 Wait on Burst
T1
TIW
T1
(Continued)
TIW
T2
In
79
T2B
T2
In
In
TBW
T2B
In
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