pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 37

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
1.0 Introduction
External Memory Mapping into Shared BIOS Memory
When the shared BIOS memory is enabled using the SHBM strap input (SHBM=1) or the Shared Memory Configuration
Registers (LDN=10h), the Expansion Memory address range is mapped into the address range of the host. The PC87591x
uses the wrap-around effect of the core address space (on a 2 Mbyte boundary) using “growing down” addresses, which
enables the host to view the Expansion flash as a continuation of the BIOS Memory. See Section 5.3.2 on page 297 for de-
tails of the memory mapping scheme.
Accessing I/O Expansion Space
The I/O expansion protocol enables implementing I/O devices or GPIO ports in the system, in addition to those available on-
chip, for IRD, OBD and DEV environments. In addition, in DEV environment, some of the on-chip I/O port pins are used to
interface with off-chip peripherals. In such a case, the I/O expansion protocol is used to implement the functionality of these
I/O ports, using off-chip external logic. Access to these ports is through the same addresses used for the ports’ on-chip im-
plementation.
128 K
64 K
56 K
64 K
1 M
2 M
2 M
1 M
4 K
Figure 8. Expansion Memory (Zone 0) Address Range - PC87591E and PC87591S
0
0
Core Address Map
Core Address Map
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(Continued)
Figure 9. Expansion Memory (Zone 0) Address Range - PC87591L
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Expansion Memory Address
Expansion Memory Address
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1 M
0
0
1 M
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