pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 282

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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5.0 Host Controller Interface Modules
5.1.4
Some register bits affect PM channel 1 to achieve firmware compatibility with the PC87570.
For a summary of the abbreviations used for Register Type, see Section 2 on page 34.
Core Interface Register Map
Host Interface Control Register (HICTRL)
The HICTRL is used in setting host interface mechanism options. On reset, non-reserved bits of HICTRL are cleared.
Location: 00 FEA0
Type: R/W
Bit
Name
Reset
Bit
0
1
2
3
4
Core Interface Registers
OBFKIE (Output Buffer Full Keyboard Interrupt Enable).
0: IRQ1 is controlled by IRQ1B bit in HIIRQC register
1: Enables the Output Buffer Full interrupt to the keyboard driver of the host processor (IRQ1). The interrupt is
OBFMIE (Output Buffer Full Mouse Interrupt Enable).
0: IRQ12 is controlled by IRQ12B bit in HIIRQC register
1: Enables the Output Buffer Full interrupt to the mouse driver in the host processor (IRQ12). The interrupt is trig-
OBECIE (Output Buffer Empty Core Interrupt Enable).
0: Interrupt signal is low
1: Enables the Output Buffer Empty interrupt to the core ICU for the keyboard/mouse channel. The interrupt signal
IBFCIE (Input Buffer Full Core Interrupt Enable).
0: Interrupt signal is low
1: Enables the Input Buffer Full interrupt to the core ICU for the keyboard/mouse channel. The interrupt signal is
PMIHIE (PMI Channel 1 Host Interrupt Enable).
0: IRQ11 is controlled by IRQ11B bit in HIIRQC register
1: Enables the Output Buffer Full interrupt of PM channel 1 in PC87570 Compatible mode, to drive the host pro-
triggered by a core write to HIKDO register and sent according to IRQM field and IRQNPOL bit in HIIRQC reg-
ister.
gered by the core write to HIMDO register and sent according to IRQM field and IRQNPOL bit in HIIRQC reg-
ister.
is active when the output buffer is empty (i.e., the interrupt signal is set (1) when OBF bit is cleared).
active when the input buffer is full (i.e., the interrupt signal is set (1) when IBF bit is set).
cessor interrupt. The interrupt is noted as IRQ11 and may be routed to any of the IRQs, to SMI or to the SCI
events. The interrupt is triggered by a core write to HIPM0DO register and sent according to IRQM field and
IRQNPOL bit in HIIRQC register.
Reserved
16
HICTRL
HIIRQC
HIKMST
HIKDO
HIMDO
HIKMDI
7
0
Mnemonic
PMICIE
6
0
Host Interface Control
Host Interface IRQ Control
Host Interface Keyboard/Mouse Status
Host Interface Keyboard Data Out Buffer
Host Interface Mouse Data Out Buffer
Host Interface Keyboard/Mouse Data In Buffer
PMIOCIE
5
0
Register Name
(Continued)
PMIHIE
Description
282
4
0
IBFCIE
3
0
OBECIE
2
0
Type
R/W
R/W
R/W
WO
WO
RO
OBFMIE
1
0
OBFKIE
Revision 1.07
0
0