pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 135

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
4.7.2
The clock source unit, as shown in Figure 45, contains two clock selectors for each counter and a 5-bit clock pre-scaler.
Pre-Scaler
The 5-bit clock pre-scaler consists of a pre-scaler register and a 5-bit counter, allowing the timer to run with a prescaled
clock. The system clock is divided by the value contained in TnPRSC+1. The minimum counter clock frequency is thus the
system clock divided by 32, and the maximum counter clock frequency is equal to the system clock. The pre-scaler register,
TnPRSC, can be read or written by software at any time. The pre-scaler counter is a 5-bit down counter which can not be
read or written by software. The 5-bit counter and the pre-scaler register TnPRSC are cleared on reset
External Event Clock
The TBn I/O pin can be selected as an external event input clock source for either of the two 16-bit counters. The polarity of
the input signal is programmable to trigger a count if either a rising or a falling edge is detected on TBn. The minimum pulse
width of the external signal is one system clock cycle; thus the maximum frequency with which the counter can run in this
mode is limited to half the system clock frequency.
Note: An External Event clock is not available in Dual Channel Capture mode because this mode requires TBn as an input.
Pulse Accumulate Mode
In Pulse Accumulate mode, the counter can also be clocked while an external signal on TBn is either high or low. In this
configuration, the output of the pre-scaler is gated with an external signal applied on TBn input. This mode can be used to
obtain a cumulative count of pre-scaler output clock pulses, as shown in Figure 46.
Note: Pulse Accumulate mode is not available in Dual Channel Capture mode because this mode requires TBn as an input.
Slow-Speed Clock
A slow-speed clock of 32.768 KHz can be used as a clock source for the two 16-bit counters. The MFT16 synchronizes the
slow-speed clock with the system clock. Therefore, the maximum input frequency of the slow-speed clock is the system clock
rate divided by four.
Some power save modes stop the system clock completely. When this occurs, the timer stops counting the slow-speed clock
until the system clock resumes. While operating in a power-save mode that uses a slow system clock, the slow-speed clock
source for the timer can only be used if it is at least four times faster than the slow- speed clock for the counter.
TBn
Slow Speed
Clock
System
Reset
Clock
Clock Source Unit
Synchr.
Pre-Scaler Counter
Synchr.
Pre-Scaler Register
5-Bit
TPRSC
Figure 45. Clock Pre-Scaler and Selector
(Continued)
135
No Clock
Accumulate
Prescaled
External
Clock
Event
Pulse
Counter 1
Counter 2
Select
Clock
Select
Clock
Counter 1
Clock
Counter 2
Clock
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