pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 36

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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1.0 Introduction
Accessing Expansion Memory
Expansion Memory Configuration is available in PC87591x versions packed in 176-pin packages. Access to it is enabled
only after:
The interface signals to the Expansion Memory are:
Figure 8 shows the External Memory Address Range mapping to the core, in the PC87591E and PC87591S devices.
Figure 9 shows the External Memory Address Range mapping to the core in the PC87591L device. Note that in PC87591L
devices, the External Memory is aliased to low addresses of the core address space, enabling access to memory locations
in the flash from both an address in the low memory and an address in the upper part of the memory.
PC87591L
Flash Size
The pins used for the memory interface are configured to operate as Expansion Memory interface signals (see
Section 2.4 on page 54 for details on the alternate functions configuration).
The BIU Zone 0 Configuration register (SZCFG0), which controls the memory access parameters (e.g., bus width and
access time), is set to support the configuration in use.
8-bit flash or SRAM: SEL0, RD, WR0, D0-7 and A0-19 (fewer address lines may be used with a smaller flash).
16-bit flash or SRAM: SEL0, RD, WR0-1, D0-15 and A1-19 (fewer address lines may be used with a smaller flash).
64 K
2 M
1 M
4 K
Core Address Map
0
(Continued)
Figure 7. Base Memory Address Mapping - PC87591L
4 K
On-Chip Base Memory
36
Off-Chip Base Memory
00 0FFF
00 0000
Access Time
Zone 1
Control
Revision 1.07