pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 86

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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4.0 Embedded Controller Modules
4.1.11 Usage Hints
The following usage hints help configure the BIU to maximize PC87591x performance and avoid contention on the data bus.
1. In IRE environment, access time to the internal flash can use zero wait and zero hold cycles or fast reads depending on
2. To avoid contention on the data bus when a read bus cycle (no T
15-12 Reserved.
Bit
10
11
the CLK frequency set for the core and its peripherals (see “Flash Read, Write and Erase Time” on page 222).
Flash sections 0 and 1 (fast zone) and Section 2 (slow zone) can use a fast read bus cycle through the operation fre-
quency of the PC87591x; therefore, program SZCFG1 fields to be: WAIT=000, HOLD=00, BRE=0, WBE=0, BW=1,
FRE=1.
When Section 2 (slow zone) can operate with a fast read bus cycle, program SZCFG2 fields to be: WAIT=000,
HOLD=00, BRE=0, WBE=0, BW=1, FRE=1.
When Section 2 (slow zone) needs to operate with normal read and zero wait, program SZCFG2 fields to be: WAIT =000,
HOLD=00, BRE=0, WBE=0, BW=1, FRE=0.
cycle in another zone, program IPST and IPRE in the different memory (I/O) zones as follows:
IPRE (Idle Before Bus Cycle). Inserts an idle cycle before the current bus cycle when this bus cycle is in a new
zone.
0: No idle cycle inserted
1: Idle cycle inserted
FRE (Fast Read Enable).
0: Disabled - Normal read bus cycle takes at least two clock cycles
1: Enabled - Normal read bus cycle takes one clock cycle
1. Set IPRE when the zone is con-
2. An IPRE is forced always for
Zone I/O
figured for fast read.
Zone I/O.
Zone 0
Zone 1
Zone 2
Zone
(Continued)
Description
86
IPRE
0/1
1
0
1
2
1
hold
clock cycles) in one zone is followed by a read bus
IPST
0
0
0
0
Revision 1.07