pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 297

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Host Controller Interface Modules
5.3
The PC87591x on-chip flash can be shared by the host and the core. It may also be used by the host for BIOS code storage
or other purposes. The on-chip flash resides in the core domain. In IRE and OBD environments, it is accessible via the core
bus. For host accesses, the flash is mapped to the host memory address space via the host interface, and a bridge is pro-
vided between the host bus and the core bus. The bridge functionality includes:
In addition, the PC87591x supports expansion memory controlled by the core domain’s Bus Interface Unit (BIU). The bridge
also supports host accesses to the expansion memory (including read/write protection on these accesses). These accesses
can occur in IRE, OBD and DEV environments.
In the PC87591S, the Shared Memory and Security module also includes a Random Number Generator (RNG). The output
of the RNG is available to the core.
5.3.1
A core bus transaction is generated for each of the following types of host bus transactions:
Memory and FWH memory read/write transactions drive Long Wait on the Sync field until the transaction is completed on
the core bus. Section 5.3.3 on page 300 describes the Sync field for indirect memory read/write transactions. Section 5.3.5
on page 301 describes the behavior for restricted accesses.
The host bus transaction is forwarded to the core bus after the following is done:
Note that host bus read transactions are translated to read transactions on the core bus, and host bus write transactions are
translated to write transactions on the core bus. Translated reads and writes behave the same as reads and writes by the
core. When the erase bit is set and the on-chip flash is enabled and addressed, the effect of a write is the same as a write
after the page erase bit is set.
5.3.2
Section 6.1.11 on page 349 describes in detail the host domain addresses for which the core bus generates transactions.
In general, the BIOS memory on the host bus can occupy one of three regions in the memory space (see Table 60 on
page 350).
Address translation between the host and the core domains is performed for host memory and FWH memory transactions.
The 32-bit address received from the host bus is used to decode the different zones, as described in Section 6.1.11 on
page 349. The address is then translated to the core bus address using the following rules:
Memory mapping between host domain address space and core domain address space
Host bus to core bus transaction bridging
Locking mechanism between host and core domains to maintain coherence of on-chip flash contents during updates
Read/write protection on host accesses to the on-chip flash
Host-accessible control and status registers of on-chip flash
Signaling interface for host-core communication associated with memory updates
8-bit memory read/write
8-bit FWH memory read/write
8-bit indirect read/write transactions, using I/O read/write to access the shared flash (see Section 5.3.3 on page 300)
Address is translated
The translated address and the access type are verified to be both:
— In core domain’s base memory or expansion memory spaces
— Unprotected
For writes (erase/program): on-chip flash is unlocked (HLOCK bit in SMCCST register is set)
Legacy and Extended Legacy BIOS Range
Handle only when enabled (see Section 6.1.11 on page 349 for the enabling alternatives); otherwise, transactions to
this zone are ignored. The address is converted to a shared memory internal address as follows:
User Defined Shared Memory Space
This address range is handled only when enabled (see Section 6.1.11 on page 349 for the enabling alternatives);
otherwise, transactions to this zone are ignored. The address translation depends on the window size defined. When
the window size is 2
LPC address are replaced with 1. The address is converted to an internal address as follows:
SHARED MEMORY AND SECURITY
Host Bus to Core Bus Access Translation
Memory Mapping and Host Address Translation
SM_Host_Address[31-0] = {1111 1111 1111 111, Host_Memory_Address[16-0]}
SM_Host_Address[31-0] = {1111 ... ... 1, Host_Memory_Address[n-0]}
n
bytes, the lower ‘n’ bits are taken from the memory address, and the upper 32
(Continued)
297
n bits of the
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