pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 367

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Host-Controlled Modules and Host Interface
Year Register (YER)
Location: Index FF
Type: R/W
RTC Control Register A (CRA)
This register controls test selection, among other functions and cannot be written before reading bit 7 of the CRD register.
Location: Index 0A
Type: R/W
Bit
Name
Reset
Bit
Name
Reset
7-0
3-0
6-4
Bit
Bit
7
Year Data. Values may be 00 to 99 in BCD format or 00 to 63 in binary format.
Periodic Interrupt Rate Select. These R/W bits select one of 15 output taps from the clock divider chain to
control the rate of the periodic interrupt (see Table 67 on page 368 and Figure 115 on page 358). They are
cleared to 000
Divider Chain Control. These R/W bits control the configuration of the divider chain for timing generation and
register bank selection (see Table 66). They are cleared to 000
Update in Progress. This RO bit is not affected by reset; it is 0 when bit 7 of CRB register is 1.
0: Timing registers not updated within 244 s
1: Timing registers updated within 244 s
Update in
Progress
16
16
7
0
7
0
CRA6
2
DV2
as long as bit 7 of CRD register is 0.
0
0
0
1
1
6
0
6
0
Divider Chain Control 2-0
Table 66. Divider Chain Control and Test Selection
CRA5
DV1
0
1
1
0
1
5
0
5
1
CRA4
DV0
X
0
1
X
X
Description
Description
367
4
0
4
0
Year Data
Oscillator Disabled
Normal Operation
Test
Divider Chain Reset
(Continued)
2
3
0
3
0
as long as bit 7 of CRD register is 0.
Configuration
Periodic Interrupt Rate Select 3-0
2
0
2
0
1
0
1
0
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0
0
0
0