pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 85

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
4.0 Embedded Controller Modules
Static Zone Configuration Register (SZCFGn)
The SZCFGn register (where n = 0, 1 or 2) controls the configuration of zone n. On reset, SZCFGn is initialized to 069F
Location: Zone 0 - 00 F984
Type: R/W
Bit
Name
Reset
2-0
4-3
Bit
5
6
7
8
9
WAIT. Number of TIW clock cycles that extend the bus cycle. Ignored when bit 11 (FRE) of this register is set
to 1.
Bits
2 1 0
0 0 0:
0 0 1:
0 1 0:
0 1 1:
1 0 0:
1 0 1:
1 1 0:
1 1 1:
HOLD. Number of T
Bits
4 3
0 0:
0 1:
1 0:
1 1:
BRE (Burst Read Enable). Ignored when bit 11 (FRE) of this register is set to 1.
0: Disabled
1: Enabled
WBR (Wait on Burst Read). Determines if a wait state (TBW) is added on a burst read transaction.
0: No TBW
1: TBW
BW (Bus Width). Sets the external bus width used for the I/O zone. It is initialized during reset to its default
value.
0: 8-bit bus
1: 16-bit bus (default)
Reserved.
IPST (Idle After Bus Cycle). Determines if an idle cycle follows the current bus cycle when the next bus cycle
is in a different zone.
0: No idle cycle inserted
1: Idle cycle inserted
Zone 1 - 00 F986
Zone 2 - 00 F988
15
0
Number
None
One
Two
Three
Number
None
One
Two
Three
Four
Five
Six
Seven
Reserved
14
0
16
16
16
13
0
hold
clock cycles.
12
0
FRE IPRE IPST Res
11
0
10
(Continued)
1
9
1
Description
85
8
0
BW WBR BRE
7
1
6
0
5
0
4
1
HOLD
3
1
2
1
WAIT
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1
1
0
1
16
.