pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 148

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
4.8.3
The PWM module supports duty cycles in the range of 0% to 100%.
The PWMi output signal cycle time is:
where:
The PWMi output signal duty cycle (in %, when INVPi is 0) is:
Special cases:
When Inverse PWMi bit is 1, the value of PWMi output is inverted. i.e., in the period described as 1 is 0 and vice versa.
4.8.4
The PWM is in Low Power mode when Power Mode bit (PWR) in PWM Control Register (PWMCNT) is 0. In this mode, the
PWM input clock is disabled (stopped), but the registers are accessible and maintained. The PWMi signal is 0 when INVPi
bit is 0; it is 1 when INVPi bit is 1.
The PWM is in normal power mode when PWR bit in PWMCNT register is 1. In this mode, the PWM module is enabled, its
registers are accessible and its clock is functional.
The PRSC and CTR registers should be updated during Low Power mode. Otherwise, there may be unpredictable transient
behavior.
4.8.5
For a summary of the abbreviations used for Register Type, see “Register Abbreviations and Access” on page 34.
PWM Register Map
Clock Pre-Scaler Register (PRSC)
The PRSC register controls the cycle time and the minimal pulse width. PRSC is cleared (00
Location: 00 FD00
Type: R/W
Bit
Name
Reset
7-0
Bit
(PRSC + 1) x (CTR + 1) x T
T
The cycle time may range from 2 x T
(DCRi + 1) / (CTR + 1) x 100.
If the DCRi value is greater than the CTR value, PWMi signal is always low.
If DCRi value is equal to the CTR value, PWMi signal is always high.
CLK
Cycle Time and Duty Cycle Calculation
Power Modes
PWM Registers
Pre-Scaler Divider Value. The divider of the PWM input clock is the number defined by PRSC7-0 + 1, e.g., a
value of 0016 results in a divide by 1, a value of FF16 results in a divide by 256.
The contents of this register may be changed only when the PWM module is in Low Power mode. Otherwise,
there may be unpredictable results.
is the core domain clock cycle time (i.e., the PWM input clock).
16
7
0
PRSC
CTR
DCRi
PWMPOL
PWMCNT
Mnemonic
CLK
6
0
Clock Pre-Scaler
Cycle Time
Duty Cycle 0 to 7
PWM Polarity
PWM Control
CLK
(Continued)
to 65536 x T
5
0
Register Name
CLK
Description
148
4
0
.
PRSC7-0
3
0
2
0
Type
R/W
R/W
R/W
R/W
R/W
16
) on reset.
1
0
Revision 1.07
0
0