pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 154

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
In Synchronous mode, Transmit Shift register (TSFT) and Transmit Buffer register (UTBUF) double buffer data for transmis-
sion. To transmit a character, a data byte is loaded into TBUF register. The data is then transferred to TSFT register. The
TSFT shifts out one bit of the current character, LSB first, on each rising edge of the clock. While the TSFT is shifting out
the current character on the UTXD pin, UTBUF register can be loaded by the software with the next byte to be transmitted.
When TSFT completes transmitting the last stop bit within the current frame, the contents of UTBUF are transferred to TSFT
register, and the Transmit Buffer Empty flag (TBE) is set. The TBE flag is automatically reset by the USART when the soft-
ware loads a new character into UTBUF register. During transmission, XMIP bit is set high by the USART. This bit is reset
only after the USART has sent the last frame bit of the current character and UTBUF register is empty.
Receive Shift register (RSFT) and Receive Buffer register (URBUF) double buffer the data being received. Serial data input
on the URXD pin is shifted into RSFT register at the first falling edge of the clock. Each subsequent falling edge of the clock
causes an additional bit to be shifted into RSFT register. The USART assumes a complete character has been received after
the correct number of rising edges on USCLK (based on the selected frame format) has been detected. On receiving a com-
plete character, the contents of RSFT register are copied into URBUF register, and Receive Buffer Full flag (RBF) is set.
The RBF flag is automatically reset when software reads the character from URBUF register.
The transmitter and receiver may be clocked from either an external source available on the USCLK pin or the internal baud
rate generator. If the internal baud rate generator is used, the baud clock is output on the USCLK pin.
Attention Mode
Attention mode is available for networking this device with other processors. This mode requires the 9-bit data format with
no parity. The number of start/stop bits are user selectable. In this mode, two types of 9-bit characters are sent on the net-
work: address characters consisting of eight address bits and a “1” (one) in the ninth bit position and data characters con-
sisting of eight data bits and a “0” (zero) in the ninth bit position.
While in Attention mode, the USART receiver monitors the communication flow but ignores all characters until an address
character is received. On the receipt of an address character, the contents of Receive Shift register are copied to the receive
buffer. The RBF flag is set and an interrupt (if enabled) is generated. The ATN bit is automatically reset to zero, and the
USART begins receiving all subsequent characters. The software must examine the contents of URBUF register and re-
spond by accepting the subsequent characters (by leaving the ATN bit reset) or waiting for the next address character (by
setting the ATN bit again).
The operation of the USART transmitter is not affected by the selection of this mode. The value of the ninth bit to be trans-
mitted is programed by setting the STPXB9 bit appropriately. The value of the ninth bit received is read from the RB9 bit.
Diagnostic Mode
This mode is available for diagnostic tests of the USART. In this mode, the UTXD and URXD pins are internally connected,
and data that is shifted out of Transmit Shift register is immediately transferred to Receive Shift register. This mode supports
only the 9-bit data format with no parity. The number of start and stop bits is user selectable.
Frame Format Selection
The format shown in Figure 55 consists of a start bit, seven data bits (excluding parity) and one or two stop bits. If parity bit
generation is enabled by setting the PEN bit, a parity bit is generated and transmitted following the seven data bits.
USCLK
UTXD
URXD
Figure 54. USART Synchronous Communication
(Continued)
Sample Input
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Revision 1.07