pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 196

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
4.13 ACCESS.BUS (ACB) INTERFACE
The PC87591x includes two ACCESS.bus interface modules. The registers of each module are prefixed with ACBn, where
‘n’ is module number 0 or 1. The signal names are suffixed with ‘n’.
Each ACCESS.bus (ACB) interface is a two-wire serial interface that is compatible with the ACCESS.bus physical layer. It
is also compatible with Intel’s SMBus and Philips’ I
and can maintain bidirectional communication with multiple master and slave devices. As a slave device, the ACB module
may issue a request to become the bus master.
The ACB interface provides full support for a two-wire ACCESS.bus synchronous serial interface. It permits easy interfacing
to a wide range of low-cost memories and I/O devices, including EEPROMs, SRAMs, timers, A/D converters, D/A convert-
ers, clock chips and peripheral drivers.
4.13.1 Features
4.13.2 Functional Description
The ACCESS.bus protocol uses a two-wire interface for bidirectional communication between the ICs connected to the bus.
The two interface lines are the Serial Data Line (SDL) and the Serial Clock Line (SCLn). These lines should be connected
to a positive supply via a pull-up resistor and remain high even when the bus is idle.
The ACCESS.bus protocol supports multiple master and slave transmitters and receivers. Each IC has a unique address
and can operate as a transmitter or a receiver. Some peripherals are receivers only.
During data transactions, the master device initiates the transaction, generates the clock signal and terminates the transac-
tion. For example, when the ACB initiates a data transaction with an attached ACCESS.bus-compliant peripheral, the ACB
becomes the master. When the peripheral responds and transmits data to the ACB, their master/slave (data transaction ini-
tiator and clock generator) relationship is unchanged even though their transmitter/receiver functions are reversed.
Data Transactions
One data bit is transferred during each clock pulse. Data is sampled during the high state of the serial clock (SCLn). Con-
sequently, throughout the clock’s high period, the data should remain stable (see Figure 69). Any change on the SDAn line
while SCLn is in high state during a transaction causes the current transaction to abort. New data should be sent during the
low SCLn state. This protocol permits a single data line to transfer both command/control information and data, using the
synchronous serial clock.
Each data transaction is composed of a Start Condition, a number of byte transfers (set by the software) and a Stop Condi-
tion to terminate the transaction. Each byte is transferred with the most significant bit first. An Acknowledge signal must fol-
low each byte (8 bits). The following sections provide further details of this process.
ACCESS.bus, SMBus and I
ACCESS.bus master
ACCESS.bus slave
— One or two user-defined addresses
— Global (broadcast) address
— ARP address
Supports polling- or interrupt-controlled operation
Generates a wake-up signal on detection of a Start Condition in Power-Down mode
Optional internal pull-up on SDAn and SCLn pins
2
C compliant
SDAn
SCLn
(Continued)
Figure 69. Bit Transfer
Data Line
Stable:
Data Valid
2
C bus. The module can be configured as either a bus master or slave
196
Change
of Data
Allowed
Revision 1.07