pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 289

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
5.0 Host Controller Interface Modules
When data is written to HIPMnDOM register, the OBF flag and the internal OBF_SMI flag are set and an SMI interrupt is
generated. The OBF_SMI flag is cleared when OBF flag is cleared. The SMI is generated as a pulse whose width is defined
by PLMM in HPIMnIC register.
The SMI interrupt is routed to the SMI pin only if both HSMIE and SMIE bits in HIPMnIE register are set. When SMIE is set
and HSMIE is cleared, SMIB in HIPMnIC register is used as the PMnSMI signal value. When SMIE is cleared, the PMnSMI
signal is inactive (high).
When data is written to HIPMnDOC register, the OBF flag and OBF_SCI internal flag are set and an SCI interrupt is gener-
ated. OBF_SCI is cleared when OBF is cleared. The SCI is generated as a pulse whose width is defined by PLMS in
HPIMnCTL register.
When data is read from HIPMnDIC register, the IBF flag is cleared, the IBF_SCI Internal flag is set and an SCI interrupt is
generated. The IBF_SCI flag is cleared when the IBF is set again. The SCI is generated as a pulse whose width is defined
by PLMS in HPIMnCTL register. Reading from HIPnDI register clears the IBF flag but does not generate an SCI interrupt.
Note that IBF_SCI flag may also be set by writing a 1 to SCIIS bit in HIPMnIC register. This is done to start an SCI interrupt
on input buffer empty without a read operation from the input buffer.
The SCI interrupt is routed to the SCI pin only if HSCIE and SCIE in HIPMnIE register are set. When SCIE is set and HSCIE
is cleared, the value of SCIB in HIPMnIC register is used as the PMnSCI signal value. When SCIE is cleared, PMnSCI is
inactive (high).
Status Read
The status of the PM channel data buffers can be read by both the host and the core. Bits 2 and 4-7 can be written by the core.
The host processor should read the Status register I/O address (legacy 66
register. The core software should read/write the HIPMnST register to access the same information. The format of the Status
register is identical for both the host and the core; see “Host Interface PM n Status Register (HIPMnST)” on page 291.
HIPMnDO (write)
HIPMnDOM (write)
HIPMnDOC (write)
SCIIS bit (HPMnIC)
HIPMnDIC (read)
HIPMnDI (read)
(HIPMnST)
OBF bit
(write 1)
IRQB bit (HIPMnIC)
IRQM field (HIIRQC)
Hardware
Interrupt
IRQB bit (HIPMnIC)
set OBF_no_int
set OBF_SCI
set OBF_SMI
clear IBF bit (HIPMnST)
(write)
set IBF_SCI
Figure 98. IRQ, SCI and SMI Control, Enhanced PM Mode
(read)
IRQNPOL bit (HIIRQC)
IRQB bit (HIPMnIC)
SCIB bit (HIPMnIC)
PLMS field (HIPMnCTL)
SMIB bit (HIPMnIC)
PLMM field (HIPMnIC)
1
0
Pulse Shape
Pulse Shape
(Continued)
HIRQE bit (HIPMnIE)
289
HSMIE bit (HIPMnIE)
HSCIE bit (HIPMnIE)
1
0
1
0
1
0
16
SCIB bit (HIPMnIC) (read)
SMIE bit (HIPMnIE)
IRQE bit (HIPMnIE)
, for channel 1) to obtain the contents of the Status
SCIE bit
(HIPMnIE)
SMIB bit (HIPMnIC)
PMnECSCI of
other channel
(read)
SCIPOL bit (HIPMnCTL)
1
SMIPOL bit (HIPMnIC)
1
0
0
SuperI/O
Routing
(Part of
Module)
PMnECSCI
Polarity
Config
IRQ
and
Gathering
Source
SMI
www.national.com
Serializer
PMnSMI
IRQ
ECSCI