pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 130

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
PS/2 Control Register (PSCON)
The PSCON register is an 8-bit read/write register. It controls the operation of the PS/2 interface by enabling it and controlling
the data transfer direction. On reset, PSCON is set to 00
Location: 00 FE84
Type: R/W
Bit
Name
Reset
3-2
5-3
Bit
Bit
0
1
6
7
ACH (Active Channel). Defines which of the PS/2 channels is currently active (i.e., a start bit was detected). In
case more than one channel become active simultaneously, only the one with the highest priority (lowest
number) is flagged.
Bits
5 4 3
0 0 0:
0 0 1:
0 1 0:
1 0 0:
1 0 1:
RFERR (Receive Frame Error).
When set to 1, indicates that the stop bit in a received frame was detected low instead of high.
Reserved.
EN (Shift Mechanism Enable).
0: The hardware shift mechanism is disabled and the software controls and monitors the PS/2 signals using
1: The hardware shift mechanism is enabled. The enabled channels are controlled by PSOSIG, and Transmit/Re-
XMT (Transmit Enable).
0: Receive mode.
1: Causes the PS/2 interface to enter Transmit mode.
HDRV (High Drive). Defines the quasi-bidirectional buffers’ behavior on transition from low to high. HDRV
defines the period of time for which the output is pulled high with a low-impedance drive (when the PC87591x
changes the output level from low to high). This period is a function of the PC87591x clock as follows:
Bits
3 2
0 0:
0 1:
1 0:
1 1:
PSOSIG and PSISIG registers.
ceive mode is controlled by the XMT bit.
Description
Disabled
Low-impedance drive for one clock cycle
Low-impedance drive for two clock cycles
Low-impedance drive for three clock cycles
WPUEN
16
Description
None of the channels is active
Channel 1
Channel 2
Channel 3
Channel 4
7
0
6
0
(Continued)
IDB
5
0
16
.
Description
Description
130
4
0
3
0
HDRV
0
2
XMT
1
0
EN
Revision 1.07
0
0