pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 308

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Host Controller Interface Modules
Shared Memory Core Top Address Register (SMCTA)
This register provides information about the size of the on-chip main block. The register is loaded with its default value on
V
Location: 00 F902
Type: RO in IRE and OBD environments
Shared Memory Host Semaphore Register (SMHSEM)
This register provides eight semaphore bits between the core and the host. Four of the bits may be set by the host; four may
be set by the core. The register is cleared (00
Location: 00 F904
Type: Varies per bit
CC
4-3
Bit
Bit
Name
Reset
Bit
Name
Reset
4-0
7-5
Bit
5
6
7
Power-Up reset only.
R/W in DEV environment
HERES (Host Error Response). Controls response type on read/write from/to a protected block or out-of-range
address. An out-of-range address is an address that the LPC configuration module defines as mapped to the
PC87591x, but it is actually translated to a reserved address in the core address space.
Bits
4 3
0 0:
0 1:
1 0:
1 1:
HLOCK (Host Lock).
0: The bridge does not generate write transactions on the core bus
1: The bridge can generate write transactions on the core bus
This bit should be set only when FMBUSY bit is cleared (see ”Flash Memory Status Register (FLSR)” in
Section 4.16.7 on page 228).
HSEMW (Host Semaphore Write). The bit is set (1) when the host writes to HSEM register. Writing 1 to this
bit position clears it to 0. Writing 0 has no effect.
HSEMIE (Host Semaphore Interrupt Enable). When the bit is set (1), the interrupt to the core is set (level
high) if HSEMW is set.
MBSD (Main Block Size Definition). Defines the size of the main block in 64 Kbyte units. Thus the MBTA value
is MBSD * 1 0000
The reset value of this field is affected by the Force MBTA Zero bit in the protection word (see Section 4.16.6 on
page 226). When the Force MBTA Zero bit is set, the reset value of this field is 0
reset value is as shown in the bit table, above.
This field is loaded on V
loaded with a new value.
Reserved.
Description
Drive Long Wait for read; ignore write
Read back 00
Drive error SYNC for both read and write
Reserved
CSEM3
16
16
7
7
0
0
16
Reserved
. Note that MBTA is actually the first address beyond the main block.
16
CSEM2
; ignore write
CC
6
6
0
0
Power-Up reset with the on-chip flash size. In DEV environment, the MBSD may be
CSEM1
16
5
0
5
0
) on reset.
(Continued)
CSEM0
Description
Description
308
4
4
0
HSEM3
2 (see note in field description)
3
3
0
HSEM2
MBSD
2
2
0
16
; when the bit is cleared, the
HSEM1
1
1
0
HSEM1
0
0
0
Revision 1.07