pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 277

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
5.0 Host Controller Interface Modules
This chapter describes functions that serve as an interface between the host and core domains. The functions are:
5.1
The PC87591x supports a standard Keyboard and Mouse Controller interface. This interface implements legacy ports 60
and 64
5.1.1
5.1.2
The PC87591x supports a keyboard/mouse communication channel that uses the standard command/status register and
data registers. It uses either polling- or interrupt-driven communication schemes with the host and/or core. The hardware is
designed to allow a race-free interface between the host and the PC87591x.
The keyboard and mouse channel consists of three registers:
Host Addresses
The host processor accesses the PC87591x Keyboard/Mouse Host Interface registers at two addresses in the host address
space. These addresses are defined by two internal chip-select signals specified in the PC87591x host configuration regis-
ters; see Section 6.1.10 on page 348). Legacy settings of these addresses are 60
data registers, respectively.
Table 42 describes the register mapping to the host processor I/O space. For simplicity, the Host Interface module specifi-
cation refers to the legacy addresses.
Core Interrupts
The Host Interface module generates four level (high) interrupts to the core ICU. These can be used by the firmware for
interrupt-driven control of the keyboard/mouse and/or PM channels.
Host Interrupts
The PC87591x Host Interface supports two interrupts to the host processor: Keyboard interrupt (legacy IRQ1) and Mouse
interrupt (legacy IRQ12). These interrupts may be controlled by hardware according to the host interface buffer status or by
the PC87591x firmware toggling the bit value.
Keyboard and
Keyboard and Mouse Controller Interface (legacy 60
Two Power Management (PM) channels compliant with ACPI EC specifications; see Section 5.2 on page 285
Shared Memory mechanism; see Section 5.3 on page 297
Core Access to SuperI/O modules; see Section 5.4 on page 313
Mobile System Wake-Up functions; see Section 5.5 on page 318
Intel 8051SL-compatible Host interface
— 8042 KBD standard interface (ports 60
— Legacy IRQ: IRQ1 (KBD) and IRQ12 (mouse) support
— Fast Gate A20 and Fast Reset via firmware
Configured using two logical devices: Keyboard and Mouse
DBBOUT - can be written by the core and read by the host processor.
DBBIN - can be written by the host processor and read by the core.
STATUS - can be read by both core and host processors. It has five bits (2, 4-7) that are written by the core. Three
other bits are controlled by the hardware to indicate the status of DBBIN and DBBOUT registers.
Mouse
16
Port
KEYBOARD AND MOUSE CONTROLLER INTERFACE
Features
General Description
.
Address
Legacy
Table 42. Mapping of the Host Interface Registers to the Host Processor
60
64
60
64
16
16
16
16
Keyboard/Mouse Command
Keyboard/Mouse Command
Keyboard/Mouse Data
Keyboard/Mouse Data
Internal Chip Select
16
, 64
16
)
16
, 64
277
16
); see Section 5.1
Write
Write
Read
Read
Type
16
Register Name
and 64
Command
Status
Data
Data
16
for the status/command and
DBBIN (A2=0)
DBBIN (A2=1)
Mnemonic
DBBOUT
STATUS
www.national.com
16