pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 235

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
4.17 POWER MANAGEMENT CONTROLLER (PMC)
The Power Management Controller (PMC) module improves the efficiency of PC87591x operation by adjusting the chip’s
power consumption to the level of activity required by the application. This module works together with the High-Frequency
Clock Generator (HCFG) and the core to control the activity of the PC87591x. It also interacts with the Multi-Input Wake-Up
(MIWU), Interrupt Control Unit (ICU) and Debugger interface for wake-up events.
4.17.1 Features
4.17.2 The Core Domain Power Modes
Table 35 summarizes the main properties of the three modes and shows the activity levels of clocks while in the various
power states.
Active Mode
In Active mode, the core domain operates at the frequency generated by the HFCG. This frequency may be changed dy-
namically using the Load, Fast, Load96 or Fast96 operations in the HFCG module. The module’s respective enable/disable
bits control module activity.
In this mode, power consumption can be reduced by selectively disabling modules and/or by the core executing the WAIT
instruction. When WAIT is executed, the core stops executing new instructions until it receives an interrupt signal.
After reset, the PC87591x is in Active mode.
Idle Mode
In Idle mode, the clock is stopped for most of the core domain. Only the PMC and a limited number of core domain modules
(such as the TWD) continue to operate at the low-frequency oscillator rate; they can wake up the core domain and resume
instruction execution when required.
For modules that are active in Idle mode, details of their activity are included in the module’s description.
Wake-up events are generated by the MIWU module according to the enabled internal and external events.
Power Off Mode
When V
the on-chip flash) and registers are not preserved in this mode. Applying power to the core domain should be done using
the V
Three core domain power modes:
— Active
— Idle
— Power Off
Two clock inputs:
— High-frequency clock (HFCLK)
— Low-frequency clock (LFCLK)
Power mode switching by software and/or hardware control
High-frequency clock source Enable/Disable control
Other core domain modules are controlled with power mode indications
CC
CC
power-up reset sequence.
power is turned off, the core domain reaches its lowest activity level. The contents of the memories (except for
Power Off
1. The RTC and TWM modules always work from the LF oscillator.
2. The core may execute the WAIT instruction while in Active mode to reduce power con-
3. Can be turned off by software but depends also on SuperI/O clock domain activation.
Active
Mode
Idle
sumption while no core activity is required. This state is referred to as “Active Executing
WAIT” in some places in the specification, but it is not a separate power state as far as
clocks are concerned.
2
On or Off
HFCG
On
Off
Table 35. Core Domain Power Mode Summary
3
(Continued)
LFCG
On
On
On
235
CLK
HF
Off
Off
LFCLK
Off
LF
LF
1
V
CC
On
On
Off
Supply
www.national.com