pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 144

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
Timer Mode Control Register (TnCTRL)
The TnCTRL register is a byte-wide read/write register. It defines the mode of operation of timer/counter and TAn and TBn
I/O pins. The register is cleared on reset.
Location: MFT16 1: 00 FD8C
Type: R/W
Bit
Name
Reset
5-3
7-6
1-0
Bit
Bit
2
3
4
5
C2CSEL (Counter 2 Clock Select). Defines the clock mode for timer/counter 2.
Bits
5 4 3
0 0 0:
0 0 1:
0 1 0:
0 1 1:
1 0 0:
Other: Reserved
Reserved.
MDSEL (Mode Select). Defines the MFT16 mode of operation.
Bits
1 0
0 0:
0 1:
1 0:
1 1:
TAEDG (TAn Edge Polarity).
0: A high-to-low transition on TAn causes the action defined by the mode of operation (e.g., input capture).
1: A low-to-high transition on TAn results in the defined action.
TBEDG (TBn Edge Polarity).
0: A high-to-low transition on TBn causes the action defined by the mode of operation (e.g., input capture or ex-
1: A low-to-high transition on TBn results in the defined action
In Pulse Accumulate mode, when this bit is set to 1, the count is enabled if TBn is high. When cleared (0) and
while operating in Pulse Accumulate mode, the counter is enabled if TBn is low.
TAEN (TAn Enable). Enables TAn to function either as a preset input or as a PWM output, depending on the
mode of operation.
If this bit is set (1), while operating in Dual Input Capture mode (mode 2), a transition on TAn causes TnCNT1
to be preset to FFFF
output. See Table 20 on page 141 for additional information.
TBEN (TBn Enable). When set (1), and while operating in either Dual Input Capture mode (mode 2) or Input
Capture and Timer mode (mode 4), a transition on TBn causes the corresponding timer/counter to be preset to
FFFF16. In mode 2, TnCNT1 is preset to FFFF16; in mode 4, TnCNT2 is preset to FFFF16. The bit has no
effect while operating in any mode other than modes 2 or 4. See Table 20 on page 141 for additional
information.
MFT16 2: 00 FDAC
ternal event count)
Reserved
Description
Mode 1
Mode 2
Mode 3
Mode 4
Description
No Clock (Counter 1 stopped)
Prescaled system clock
External Event on TBn
Pulse Accumulate
Slow-speed Clock
7
0
16
16
16
TAOUT
. In the remaining modes of operation, setting TnAEN enables TAn to function as a PWM
6
0
TBEN
(Continued)
5
0
TAEN
Description
Description
144
4
0
TBEDG
3
0
TAEDG
2
0
1
0
MDSEL
Revision 1.07
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0