pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 125

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
4.6.4
The shift mechanism is designed to off load the bit level handling of the data transfer from the firmware to a hardware
scheme; this improves system tolerance to interrupt latency. The mechanism includes a shift register and a state machine
that controls the PS/2 protocol.
Figure 41 illustrates the shift mechanism PS/2 data transfer sequence. There are three basic modes: Disabled, Receive and
Transmit. Different states in each mode define the progress of the data transfer. The rest of this section details the use of
the shift mechanism for implementing a PS/2 data transfer.
Reset the Shift Mechanism
Clearing either the shift mechanism enable bit (EN = 0 in PSCON register) or all the channels’ clock bits (CLK4-1 = 0) resets
the shift mechanism. In this state, PSTAT register is cleared (00
(PSCLK4-1 and PSDAT4-1) is set according to the value of their control bits (CLK4-1 and WDAT4-1, respectively).
When the shift mechanism is reset while in an unknown state or while in Transmit Idle state, the firmware should set (1)
WDAT4-1 before the shift mechanism is reset.
Before disabling the shift mechanism, the software should clear (0) CLK4-1 to prevent glitches on the clock signals.
Enable the Shift Mechanism
To enable the shift mechanism, verify that PSOSIG register is set to 47
puts the shift register state machine in Receive Inactive or Transmit Inactive state (XMT is 0 or 1, respectively, in PSCON
register). In either of these states, the clock signals (PSCLK4-1) are low and the data signals PSDAT4-1 are either floating
or pulled high.
Operating With the Shift Mechanism Enabled
CLK1, CLK2, CLK3
or CLK4 = 1
Transmit Mode
Transmission
EN = 0
Transmit
Transmit
Transmit
Inactive
Active
Idle
End of
Start Bit
Detected
Line Control
Bit Detected
Figure 41. Shift Mechanism State Diagram
and CLK4 = 0
CLK1, CLK2, CLK3
EN = 1 and
XMT = 1
(Continued)
XMT = 0
XMT = 1
CLK1, CLK2, CLK3
Disabled
125
and CLK4 = 0
PS/2 Reset
16
EN = 1 and
), and the state of the PS/2 clock and data signals
XMT = 0
16
and then set (1) EN bit in PSCON register. This
Receive Mode
Receive
Inactive
Receive
Receive
Reception
Active
End of
Idle
EN = 0
and/or CLK4 = 1
CLK1, CLK2, CLK3
Start Bit
Detected
Stop Bit
Detected
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