pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 287

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
5.0 Host Controller Interface Modules
Core Interrupts
For each channel, the Host Interface module generates two level (high) interrupts to the core ICU (see Figure 96). The firm-
ware can use these for interrupt-driven control of the PM channels.
In PC87570 Compatible mode (EME in HIPMnCTL register is set to 0), interrupts are enabled using HICTRL register bits
PMOCIE and PMICIE for output buffer empty and input buffer full interrupts, respectively.
In Enhanced PM mode (EME in HIPMnCTL register is set to1), interrupts are enabled using HIPMnCTL register bits OBEIE
and IBFIE for output buffer empty and input buffer full interrupts, respectively.
Host Interrupt Generation Modes
The Host Interface module generates three types of interrupts to the host: regular IRQ, SMI and SCI. The interrupt schemes
are designed to meet ACPI requirements for host interrupts. Two interrupt modes are supported: PC87570 Compatible and
Enhanced PM.
PC87570 Compatible Mode
PC87570 Compatible mode uses the same method for IRQ generation as the PC87570. It is available only for PM channel 1
and is enabled when EME in HIPMnCTL register is set to 0. Figure 98 illustrates this scheme.
The host configuration module assigns host interrupts to IRQ numbers (see Section 6.1.13 on page 355). IRQ11 is used as
an example interrupt and for the signal naming (the actual interrupt number used is determined by the IRQ routing logic).
When hardware-driven IRQ11 is disabled (PMHIE in HICTRL register is cleared), the firmware can control the IRQ11 signal
by writing to the signal’s respective bit in HIIRQC register. When hardware-driven IRQ11 is enabled (PMHIE is set to 1),
interrupts to the host are generated according to the status of the OBF flag.
Channel n
OBEIE bit (HIPMnCTL)
PMOCIE bit (HICTRL)
IBFIE bit (HIPMnCTL)
Port
1. The legacy address serves as an example only. Do not assign the same address for both channels.
PMICIE bit (HICTRL)
PM
Address
Legacy
62
66
62
66
EME bit (HIPMnCTL)
EME bit (HIPMnCTL)
16
16
16
16
OBF bit (HIPMnST)
IBF bit (HIPMnST)
1
Index 60
Index 62
Index 60
Index 62
Register Index
Table 43. Host Interface Registers to Host Processor Mapping
Configuration
1
1
0
0
16
16
16
16
Figure 96. Core Interrupt Request for PM Channel n
, 61
, 63
, 61
, 63
16
16
16
16
PM Internal Chip
Command/Status
Command/Status
(Continued)
Select
Data
Data
287
Type
Write
Write
Read
Read
PMnOBE
Interrupt
Interrupt
PMnIBF
Command
Register
Status
Name
Data
Data
Mnemonic
ICU
DBBOUT
STATUS
DBBIN
DBBIN
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