pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 204

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

www.national.com
Embedded Controller Modules
ACB Control Status Register (ACBnCST)
The ACBnCST register maintains current ACB status and controls several ACB module functions, as described below. On
reset and when the module is disabled, the non-reserved bits of ACBnCST are cleared (00
Location: Channel 1 - 00 FF64
Type: Varies per bit
Bit
Name
Reset
Bit
0
1
2
3
4
5
6
7
R/W1C BB (Bus Busy). When set (1), indicates the bus is busy. It is set either when the bus is active (i.e., a
Channel 2 - 00 FFE4
Type
R/W
RO
RO
RO
RO
RO
RO
ARPMATCH MATCHAF
BUSY. When set (1), indicates that the ACB module is in one of the following states:
– Generating a Start Condition
– In Master mode (MASTER in ACBnST register is set)
– In Slave mode (MATCH or GMATCH in ACBnCST register is set)
– In the period between detecting a Start Condition and completing the reception of the address byte;
The BUSY bit is cleared by the completion of any of the above states or by disabling the module. It
should always be written 0.
low level on either SDA or SCL) or by a Start Condition. It is cleared when the module is disabled, on
detection of a Stop Condition or by writing 1 to this bit. See Section 4.13.9 on page 207 for a
description of the use of this bit.
MATCH (Address Match). In Slave mode, MATCH is set (1) when SAEN in ACBnADDR register is
set and the first seven bits of the address byte (the first byte transferred after a Start Condition) match
the 7-bit address in ACBnADDR register. It is cleared by Start Condition, a Repeated Start or a Stop
Condition (including illegal Start or Stop Condition).
GCMATCH (Global Call Match). In Slave mode, GCMTCH is set (1) when GCMEN in ACBnCTL1
register is set and the address byte (the first byte transferred after a Start Condition) is 00
cleared by a Start Condition, a Repeated Start or a Stop Condition (including illegal Start or Stop
Condition).
TSDA (Test SDA Line). Reads the current value of the SDA line. This bit can be used while
recovering from an error condition in which the SDA line is constantly pulled low by a slave that went
out of synch. Data written to this bit is ignored.
TGSCL (Toggle SCL Line). Enables toggling the SCL line during the process of error recovery. When
the SDA line is low, writing 1 to this bit toggles the SCL line for one cycle. Writing 1 to TGSCL while
SDA is high is ignored. The bit is cleared when the clock toggle is completed.
MATCHAF (Match Address Field). When the MATCH bit is set, MATCHAF indicates with which of
the two possible slave addresses (ADDR cleared in ACBnADDR register or set in ACBnADDR2
register) the match has occurred. If both addresses match, the bit is cleared.
ARPMATCH (ARP address Match). In Slave mode, ARPMTCH is set (1) when ARPMEN in
ACBnCTL3 register is set and the address byte (the first byte transferred after a Start Condition) is
110 0001
or Stop Condition).
7
0
after this, the ACB either becomes not busy or enters Slave mode.
2
. It is cleared by Start Condition, a Repeated Start or a Stop Condition (including illegal Start
16
16
6
0
TGSCL
(Continued)
5
0
TSDA
204
4
0
Description
GCMATCH
3
0
MATCH
2
0
16
).
BB
1
0
16
BUSY
. It is
Revision 1.07
0
0