pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 257

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
Data is not inverted between the serial input and serial output of IR.
The IR parallel input status bits, loaded at the Capture IR state of any instruction scan operation, are shown below.
Instruction Register
Table 38 shows the behavior of IR in each TAP controller state.
All actions resulting from an instruction terminate when a new instruction is transferred to the parallel output of the IR (i.e.,
in Update-IR or TAP-Reset states).
All operations of the shift register stages occur on the rising edge of TCK after entry into a TAP controller state.
The data present at the parallel output of the IR is latched from the shift register stage on the falling edge of TCK in Update-
IR state.
After entry into TAP-Reset state as a result of TAP controller clocked operation, the BYPASS instruction is latched onto the
IR output on the falling edge of TCK.
Bit
Name
Reset
11-7 MSG_LEN (Message Length). Contains the Tx message length in words. When the Tx status word PID field is
6-3
Bit
0
1
2
Fixed value (1).
Fixed value (0).
RX_BUSY (Receive Busy). Busy indication from the Rx data link.
PID (Processor ID). Contains the processor ID from the Tx data link.
When TINT is set to 1 (not active), PID field is ‘1111’, indicating that the Tx link has no valid data.
When TINT is set to 0 (active), PID field indicates the value of PID field in DBGTXLOC register. Note that this
value is latched when TINT becomes active and is held until the Rx data is read by the host.
not ‘1111’, the MSG_LEN holds a copy of the MSG_LEN field in DBGTXST register. When the size of this field
is less than five bits, the MSG_LEN MSBs in the status word are forced to 0.
TAP-Reset
Capture-IR
Shift-IR
Exit1-IR
Exit2-IR
Pause-IR
Update-IR
All other states
Controller State
11
MSG_LEN
Operation
Table 38. Instruction Register Operation in Each Controller State
7
Undefined
Load status data (table 2-2)
Shift towards serial output
Retain last state
Retain last state
Undefined
6
Shift Register Stage
(Continued)
5
PID
Description
257
5
Set to give BYPASS instruction
Retain last state
Retain last state
Retain last state
Load from shift register stage
Retain last state
3
Parallel Output
RX_BUSY
2
1
0
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