pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 179

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
ADC Configuration Register (ADCCNF)
This register controls the operation and global configuration of the ADC module. ADCCNF is cleared (00
Location: 00 FF22
Type: R/W
ADC Clock Control Register (ACLKCTL)
This register controls the system clock to ADC clock division. ACLKCTL is set to 3F
Location: 00 FF24
Type: R/W
Bit
Name
Reset
Bit
Name
Reset
7-5 Reserved.
Bit
5-0
7-6
Bit
0
1
2
3
4
ADCEN (ADC Module Enable). Controls the operation of the ADC to minimize power consumption and prevent
glitch effects during configuration changes; see “Enabling and Disabling the ADC” on page 174.
0: ADC disabled (default)
1: ADC enabled
REMDEN (Remote Temperature Diode Enable). Controls the utilization of the package pins for either the
remote diode (DP, DN) or the AI8 and AI9 voltage inputs (AD8, AD9).
0: AI8, AI9 voltage inputs enabled (default) - forces RDMEASEN in TCHANCTL register to 0; only the local diode
1: Remote diode enabled - if RDMEASEN in TCHANCTL register is set, the temperature channel measures both
INTECEN (Interrupt from End-of-Cycle Event Enable). Enables generation of an ADC interrupt on an End-of
ADC-cycle event (EOCEV in ADCSTS register).
0: Disabled (default)
1: Enabled - ADC Interrupt from EOCEV
INTOTEN (Interrupt from Overtemperature Event Enable). Enables generation of an ADC interrupt on an
Overtemperature event (OTSEV in ADCSTS register).
0: Disabled (default)
1: Enabled - ADC Interrupt from OTSEV
INTOSEN (Interrupt from Open/Short Event Enable). Enables generation of an ADC interrupt on an
Open/Short event (OPSHEV in ADCSTS register).
0: Disabled (default)
1: Enabled - ADC Interrupt from OPSHEV
SCLKDIV (System Clock Division Factor). Used to divide the system clock in order to obtain the ADC clock.
The system clock frequency is set separately (see Figure 78 on page 239). The resulting ADC clock frequency
should be equal to 0.5 MHz.
Range: 4 to 63 (default is 63, decimal values); values 0 to 3 are illegal and may result in undetermined ADC behavior.
Reserved.
is measured by the temperature channel.
the remote and the local diodes in successive cycles.
16
16
7
0
7
0
Reserved
Reserved
6
0
6
0
(Continued)
5
0
5
1
INTOSEN
Description
Description
179
4
0
4
1
INTOTEN
3
0
3
1
SCLKDIV
16
INTECEN
on reset.
2
0
2
1
REMDEN
1
0
1
1
16
) on reset.
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ADCEN
0
0
0
1