pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 213
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pc87591l
Manufacturer Part Number
pc87591l
Description
Lpc Mobile Embedded Controllers
Manufacturer
National Semiconductor Corporation
Datasheet
1.PC87591L.pdf
(437 pages)
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Revision 1.07
Embedded Controller Modules
ACM Control and Status Register (ACMCTS)
This register controls the operation and indicates the status of the ACM module. ACMCTS is cleared (00
Location: 00 FD40
Type: Varies per bit
Bit
Name
Reset
7-4
Bit
0
1
2
3
R/W1C EOMEV (End-of-Measurement Event). End of voltage level measurement burst (for all eight inputs).
R/W1C EOCEV (End-of-Comparison Event). End of threshold comparison in Threshold Comparison Burst
R/W1C OVUNTHEV (Over/Under Threshold Event). At least one input is above (or below) the voltage
Type
W
START (ACM Operation Start). Start trigger for the ACM operation in the mode selected by ACMMOD
the START bit without modifying the ACMMODE value is ignored by the module.
field in ACMCNF register. If the new ACMMOD value differs from the value currently in use, all event
flags (EOMEV, EOCEV, OVUNTHEV) are cleared and operation in the new mode begins. Writing a 1 to
0: No effect - (default)
1: Operation start trigger - automatically returns to 0 after start
The bit is set only when the ACM is in Voltage Level Burst mode (ACMMOD = 01
register).
0: Measurement in progress, or not in Voltage Level Burst mode (default)
1: End of voltage level measurement burst
mode (ACMMOD = 10
0: Comparison in progress, or not in Threshold Comparison Burst mode (default)
1: End of threshold comparison
threshold value. The bit is set only when the ACM is in Low Power Threshold Comparison mode
(ACMMOD = 11
0: No input above (or below) the threshold, or not in Low Power Threshold Comparison mode (default)
1: One or more inputs above (or below) the threshold
Reserved.
16
7
0
6
0
2
Reserved
in ACMCNF register).
2
in ACMCNF register).
(Continued)
5
0
213
4
0
Description
OVUNTHEV
3
0
EOCEV
2
0
EOMEV
1
0
2
in ACMCNF
16
) on reset.
www.national.com
START
0
0
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