pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 8

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Table of Contents
4.2
4.3
4.1.4
4.1.5
4.1.6
4.1.7
4.1.8
4.1.9
4.1.10
4.1.11
DMA CONTROLLER (DMAC) ................................................................................................... 87
4.2.1
4.2.2
4.2.3
4.2.4
4.2.5
4.2.6
4.2.7
4.2.8
4.2.9
INTERRUPT CONTROL UNIT (ICU) ......................................................................................... 98
4.3.1
4.3.2
4.3.3
Early Write Bus Cycle .................................................................................................. 72
Late Write Bus Cycle ................................................................................................... 74
Normal Read Bus Cycle .............................................................................................. 76
Fast Read Bus Cycle ................................................................................................... 79
I/O Expansion Bus Cycles ........................................................................................... 80
Development Support .................................................................................................. 81
BIU Registers .............................................................................................................. 83
Usage Hints ................................................................................................................. 86
Features ...................................................................................................................... 87
Functional Description ................................................................................................. 87
Channel Assignment in PC87591x .............................................................................. 87
Transfer Types ............................................................................................................ 88
Bus Policy .................................................................................................................... 90
Operation Modes ......................................................................................................... 91
Software DMA Request ............................................................................................... 92
DMAC Registers .......................................................................................................... 92
Usage Hints ................................................................................................................. 97
Features ...................................................................................................................... 98
Non-Maskable Interrupt (NMI) ..................................................................................... 98
Maskable Interrupts ..................................................................................................... 98
(Continued)
Control Signals .................................................................................................... 72
Bus Status Signals ............................................................................................... 81
Core Bus Monitoring ............................................................................................ 82
BIU Configuration Register (BCFG) ..................................................................... 83
I/O Zone Configuration Register (IOCFG) ........................................................... 84
Static Zone Configuration Register (SZCFGn) .................................................... 85
Direct (Fly-By) Transfers ...................................................................................... 88
Indirect (Memory-to-Memory) Transfers .............................................................. 89
Intermittent Operation Mode ................................................................................ 90
Continuous Operation Mode ................................................................................ 90
Single Transfer Operation .................................................................................... 91
Double Buffer Operation ...................................................................................... 91
Auto-Initialize Operation ...................................................................................... 92
DMAC Register Map ............................................................................................ 92
Device A Address Counter Register (ADCAn) ..................................................... 93
Device A Address Register (ADRAn) .................................................................. 93
Device B Address Counter Register (ADCBn) ..................................................... 93
Device B Address Register (ADRBn) .................................................................. 93
Block Length Counter Register (BLTCn) ............................................................. 94
Block Length Register (BLTRn) ........................................................................... 94
DMA Control Register (DMACNTLn) ................................................................... 94
DMA Status Register (DMASTATn) ..................................................................... 96
External NMI Inputs ............................................................................................. 98
Non-Maskable Interrupt Processing .................................................................... 98
PFAIL Input .......................................................................................................... 98
Maskable Interrupt Vectors .................................................................................. 99
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Revision 1.07