pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 307

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Host Controller Interface Modules
5.3.9
The following set of registers is accessible only by the core. These registers are maintained by V
For a summary of the abbreviations used for Register Type, see Section 2 on page 34.
Shared Memory Core Register Map
Shared Memory Core Control and Status Register (SMCCST)
This register provides control and status of read/write from/to a restricted address. The register is cleared (00
Location: 00 F900
Type: R/W
Bit
Name
Reset
Bit
Name
Reset
Bit
3-0
7-4
Bit
0
1
2
SMCCST
SMCTA
SMHSEM
SMCORP0-2
SMCOWP0-2 Shared Memory Core Override Write Protect 0-2
RNGCS
RNGD
Shared Memory Core Registers
HRERR (Host Read Error). The bit is set (1) when the host attempts to read from a read-protected block or
out-of-range address. An out-of-range address is an address that the LPC configuration module defines as
mapped to the PC87591x, but it is actually translated to a reserved address in the core address space. Writing
1 to this bit clears it to 0. Writing 0 has no effect.
HWERR (Host Write Error). The bit is set (1) when the host attempts to write to a read-protected block or out-
of-range address. An out-of-range address is an address that the LPC configuration module defines as mapped
to the PC87591x, but it is actually translated to a reserved address in the core address space. Writing 1 to this
bit clears it to 0. Writing 0 has no effect.
HERRIEN (Host Error Interrupt Enable). When set (1) and either the HRERR or HWERR bit is set (1), a core
interrupt is generated; otherwise, the core interrupt is inactive.
Type
Mnemonic
R/W HSEM3-0. Four bits that may be updated by the host and read by both the host and the core.
RO
HSEMIE
CSEM3-0. Four bits that may be updated by the core and read by both the host and the core.
CSEM3
16
7
0
7
0
Shared Memory Core Control and Status
Shared Memory Core Top Address
Shared Memory Host Semaphores
Shared Memory Core Override Read Protect 0-2
Random Number Generator Control and Status
Random Number Generator Data
HSEMW
CSEM2
6
0
6
0
HLOCK
Register Name
CSEM1
5
0
5
0
(Continued)
CSEM0
Description
307
4
4
0
0
Description
HERES
HSEM3
3
3
0
0
RO in IRE and OBD environments;
HERRIEN
HSEM2
R/W in DEV environment
2
0
2
0
Varies per bit
Varies per bit
R/W or RO
R/W or RO
Type
R/W
RO
CC
HSEM1
HWERR
.
1
0
1
0
16
HSEM0
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) on reset.
HRERR
0
0
0
0