pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 66

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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3.0 Power, Reset and Clocks
In DEV environment, the PC87591x outputs to the BRKL_RSTO signal an indication that a reset occurred at the core
domain. See Section 4.20.3 on page 272 for the implementation and usage of RSTO.
The following sections detail the sources and effects of the various resets on the PC87591x, per reset type.
3.2.1
V
tects the status of the V
as “good” (i.e., V
For more details, see Section 6.2.9 on page 360.
3.2.2
V
applied. This reset is completed t
If the 32 KHz crystal is disabled before V
PC87591x. Any host processor access during this time results in:
On V
3.2.3
The PC87591x generates a WATCHDOG reset on request from the TWD module (i.e., a WATCHDOG signal is asserted).
It generates a Debugger Interface reset on request from the Debugger Interface module (reset command). During these re-
sets, the PC87591x performs the V
The reset periods are identical to the V
3.2.4
Warm reset is activated on the falling edge of RESET1 input. If Warm reset and V
V
PP
CC
CC
The host processor is stalled (by driving a “Long WAIT sync” response on the LPC bus) until after the reset process
is completed and the bus request can be performed.
If HRAPU bit in MSWCTL1 register is set (1), the host processor is reset by asserting KBRST until the internal reset
is completed.
Enables the 32 KHz crystal, if it is disabled.
Resets the High-Frequency Clock Generator (HFCG) to its default frequency.
Loads default values to all registers whose values are retained by V
Puts pins with strap options into TRI-STATE and enables the internal pull-downs on the strap pins.
Samples the values of the strap pins.
Resets the TAP controller of the Debugger Interface module.
Resets the MSWC, excluding those MSWC registers whose values are retained by V
Resets Port PC0.
Carries out all the Warm reset actions (see below).
The PC87591x does not sample the value of any strap pin; instead, it maintains the configuration determined by the
strap pins at V
It does not reset the TAP controller.
On Debugger I/F, reset PC0 is not reset (it is reset on WATCHDOG reset).
It resets the HFCG to its default frequency.
Some MSWC registers do not reset on WATCHDOG or Debugger I/F reset.
is an internal power signal derived from V
Power-Up reset is generated by an internal circuit. The PC87591x performs a V
power-up takes precedence.
CC
Power-Up reset, the PC87591x responds as follows:
V
V
WATCHDOG Reset and Debugger Interface Reset
Warm Reset
PP
CC
Power-Up Reset
Power-Up Reset
PP
CC
is above V
Power-Up reset.
PP
power. V
BATDTC
IRST
CC
PP
). When active, this signal resets all registers whose values are retained by V
after the internal clocks have stabilized (see Section 7.6.2 on page 384).
Power-Up reset signal is active from the rising of V
Power-Up reset actions, with the following exceptions:
CC
CC
Power-Up reset period.
(Continued)
power-up, external devices should wait at least t
CC
and V
BAT
. V
66
PP
Power-Up reset is generated by an internal circuit that de-
CC
.
CC
Power-Up reset occur at the same time,
CC
Power-Up reset when V
PP
PP
until the V
.
32KOSC
before accessing the
PP
power is detected
CC
power is
Revision 1.07
PP
.