pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 168

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

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Embedded Controller Modules
TWDT0 Control and Status Register (T0CSR)
The T0CSR register is a read/write register. It controls the operation and provides the status of the T0 timer. The non-re-
served bits of T0CSR are cleared (0) on reset.
Location: 00 FEE6
Type: R/W
WATCHDOG Count Register (WDCNT)
The WDCNT register is a byte-wide, write-only register. It holds the value loaded into the WATCHDOG counter when it is
touched and counts down from it. The WATCHDOG is started by the first write to the register. Each successive write restarts
the WATCHDOG counter. A write to WDCNT functions as a touch operation when WDSDME bit TWCFG register is cleared,
even if WDCNT is locked; in this case, the WATCHDOG counter is restarted using the value loaded in PRESET field before
WDCNT was locked (i.e., the new PRESET value is ignored). On reset this register is initialized to 0F
Location: 00 FEE8
Type: WO
WATCHDOG Service Data Match Register (WDSDM)
The WDSDM register is a byte-wide, write-only register. When WDSDME in TWCFG register is set, the WATCHDOG count-
ing restarts from the value in WDCNT, when WDSDM is written with 5C
gers a WATCHDOG signal. If RSDATA is written more than once per three WATCHDOG clock cycles, a WATCHDOG signal
is also triggered. When the WDSDME bit is cleared, a write to this register is ignored.
Location: 00 FEEA
Type: WO
Bit
Name
Reset
Bit
Name
Reset
Bit
Name
7-4
7-0
7-0
Bit
Bit
Bit
0
1
2
3
RST (Reset). When set (1), forces the timer to restart counting in the next input clock rising edge. The bit is
cleared by the input clock rising edge, indicating that the counter resumed its automatic re-triggerable operation.
Writing 0 to this bit is ignored.
TC (Terminal Count). Indicates that the counter has reached zero (terminal count). This bit is cleared each time
the register is read. It is a read-only bit and data written to it is ignored.
Reserved.
WDLTD (WATCHDOG Last Touch Delay). The bit is set when the WDCNT is written. It is cleared after
WATCHDOG is updated. (After WATCHDOG is updated, it is safe to switch to Idle mode.)
Reserved.
PRESET. Defines the counter preset value.
RSDATA.
16
16
16
7
0
7
0
7
6
0
6
0
6
Reserved
(Continued)
5
0
5
0
5
Description
Description
Description
168
4
0
4
0
4
PRESET
RSDATA
WDLTD
16
. If any other data is written to this register, it trig-
3
0
3
1
3
Reserved
2
0
2
1
2
TC
16
1
0
1
1
1
.
RST
Revision 1.07
0
0
0
1
0