pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 183

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pc87591l

Manufacturer Part Number
pc87591l
Description
Lpc Mobile Embedded Controllers
Manufacturer
National Semiconductor Corporation
Datasheet

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Revision 1.07
Embedded Controller Modules
Voltage Channel 1 Control Register (VCHN1CTL)
This register both controls the operation and indicates the status of Voltage Channel 1. VCHN1CTL is set to 1F
Location: 00 FF34
Type: Varies per bit
Bit
Name
Reset
4-0
Bit
5
6
7
R/W1C DATVAL (Data Valid). Voltage Channel 1 Data Buffer contains new data. The data may be read
Type
R/W
R/W
R/W
DATVAL
SELIN (Selected Input). Selects a voltage input to be measured during the next ADC cycle. The new
value should be set before the beginning of the channel measurement. When read, this field indicates
to which input the contents of the channel data buffer belongs. When written, it selects a new input for
the next channel measurement. See Figure 60 on page 172 for details on the channel input signals
connection to pins.
The channel is disabled by setting this field to 11111
enabling a higher measurement rate for the remaining channels (shorter ADC cycle). The DATVAL bit
is cleared
Bits
4 3 2 1 0
0 0 0 0 0:
0 0 0 0 1:
....
0 1 0 0 0:
0 1 0 0 1:
0 1 0 1 0:
....
0 1 1 0 1:
Other:
1 1 1 1 1:
INTDVEN (Interrupt from Data Valid Enable). Enables generation of an ADC interrupt on a Voltage
Channel 1, Data Valid event (End-of-conversion).
0: Disabled (default)
1: Enabled - ADC Interrupt from local DATVAL
CSCALE (Channel Scale). Controls the input scale of the input for the channel to be converted (as
selected by SELIN field).
0: Channel uses the high range scale (default)
1: Channel uses the low range scale
immediately or at the end-of-cycle. This flag is cleared when the channel is disabled, when the ADC
module is disabled (ADCEN in ADCCNF register is cleared) or by a write of 1 to it.
0: No new valid data in VCHN1DAT register (default)
1: End of conversion - new data is available in the buffer
16
7
0
CSCALE
6
0
Description
Channel 0
Channel 1
Channel 8 (Available when REMDEN bit in ADCCNF register is cleared)
Channel 9 (Available when REMDEN bit in ADCCNF register is cleared)
Channel 10
Channel 13
Reserved
Channel Disabled (default)
INTDVEN
(Continued)
5
0
183
4
1
Description
2
. When disabled, the channel is “skipped”,
3
1
SELIN
2
1
1
1
16
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on reset.
0
1

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