pc87591l National Semiconductor Corporation, pc87591l Datasheet - Page 227

• Manufacturer Part Number: pc87591l
• Description: Lpc Mobile Embedded Controllers
• Manufacturer: National Semiconductor Corporation

Revision 1.07
Embedded Controller Modules
The protection word is read by hardware from the Information Block during the internal reset process. This information is
used to set the host access restrictions described in Section 5.3.5 on page 301, the core access restrictions defined in this
section, and the JTAG access protection described in OBD and PROG environment access restrictions; see Table 30 on
page 221.
There is no protection over the core’s reading the flash contents. Writes to a write-protected page are ignored. When en-
abled, a core interrupt may be generated on write-protect violations.
Core-Initiated Accesses
There is no read protection on core-initiated read accesses. Write protection is provided with default settings and firmware
override as follows:
This protection is defined using FCWP0 register. All blocks are defined as write protected on reset. The blocks within the
Core Boot Block and Host Boot Block are read only (RO) to prevent accidental alteration of their contents by the core.
Special Erase state is not supported for core-initiated accesses.
Host-Initiated Accesses
Host access to the flash Main Block is controlled by the information in the protection word and is controlled and further re-
stricted by the core. Section 5.3.5 on page 301 details the host access limitations. The host may not access the Information
Block.
12-10 Reserved.
14-13 RST2EN (RESET2 Enable). Controls the use of the RESET2 alternate function. The following options are
9-7
Bit
15
5
6
Main memory block - per 8 Kbyte block
Information Block Factory parameters and protection word are always write protected
1. When expansion memory is used for a shared BIOS implementation, set the Force MBTA Zero bit to 0, do not
clear the Host Boot Block bit, and use a flash device with a boot block as expansion memory.
RTC Lock Default. Defines the reset value of the Lock RTC Host Access (LKRTCHA) bit in the Lock SuperI/O
Host Access register (LKSIOHA). This enables preventing host access to the RTC at any time when the RTC is
used by security applications running on the core.
0: RTC Lock is disabled on reset (LKRTCHA=0)
1: RTC Lock is enabled on reset (LKRTCHA=1) (default)
Force MBTA Zero. Enables the setting of the host boot block location to either end of on-chip flash or to the
expansion memory
0: MBSD field in SMCTA register is reset to the implemented on-chip flash size
1: MBSD field in SMCTA register is reset to 0000
Flash Contents Protect. Enables protecting the contents of the on-chip flash from probing through the JTAG
interface or Parallel interface.
Bits
9 8 7
1 1 1:
Other:
supported in the PC87591x:
Bits
15 14 Description
0 0: Reserved
0 1: RESET2 is enabled on the IOPB7/RING/PFAIL/RESET2 pin
1 0: RESET2 is enabled on the IOPD2/EXWINT24/RESET2 pin
1 1: RESET2 input is disabled, and RESET2 events will not be generated (default)
Reserved.
In OBD and DEV environments, only
Description
Flash access is enabled for both read and write
Flash access is protected. In any environment other than IRE, the device remains reset.
special erase through the JTAG interface is enabled.
1
. See “Shared Memory Core Top Address Register (SMCTA)” on page 308.
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Description
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(default)
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