mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 113

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mc68hc916y3

Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
5.3.1 Clock Sources
MC68HC16Y3/916Y3
USER’S MANUAL
MODCLK
The fast reference is typically a 4.194 MHz crystal; the slow reference is typically
32.768 kHz crystal. Each reference frequency may be generated by sources other
than a crystal. Keep these sources in mind while reading the rest of this section. Refer
to APPENDIX A ELECTRICAL CHARACTERISTICS for clock specifications.
Figure 5-2 is a block diagram of the clock submodule.
The state of the clock mode (MODCLK) pin during reset determines the system clock
source. When MODCLK is held high during reset, the clock synthesizer generates a
clock signal from an external reference frequency. The clock synthesizer control reg-
ister (SYNCR) determines operating frequency and mode of operation. When
MODCLK is held low during reset, the clock synthesizer is disabled and an external
system clock signal must be driven onto the EXTAL pin.
The input clock, referred to as f
The output of the clock system is referred to as f
normal operating limits.
To generate a reference frequency using the crystal oscillator, a reference crystal
must be connected between the EXTAL and XTAL pins. Typically, a 32.768 kHz crys-
tal is used for a slow reference, but the frequency may vary between 25 kHz to 50 kHz.
Figure 5-3 shows a typical circuit.
NOTES:
1. 128 IS PRESENT ONLY ON DEVICES WITH A FAST REFERENCE OSCILLATOR.
EXTAL
OSCILLATOR
CRYSTAL
XTAL
Figure 5-2 System Clock Block Diagram
Freescale Semiconductor, Inc.
128
For More Information On This Product,
1
COMPARATOR
Go to: www.freescale.com
PHASE
ref
, can be either a crystal or an external clock source.
SYSTEM CLOCK CONTROL
FEEDBACK DIVIDER
LOW-PASS
FILTER
XFC
sys
. Ensure that f
W
Y
X
V
ref
VCO
DDSYN
and f
SYSTEM
sys
CLOCK
MOTOROLA
are within
PLL BLOCK
CLKOUT
5-5

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