mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 122

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.3.3 External Bus Clock
5.3.4 Low-Power Operation
5-14
MOTOROLA
The state of the E-clock division bit (EDIV) in SYNCR determines clock rate for the
E-clock signal (ECLK) available on pin ADDR23. ECLK is a bus clock for MC6800
devices and peripherals. ECLK frequency can be set to system clock frequency
divided by eight or system clock frequency divided by sixteen. The clock is enabled by
the CS10PA[1:0] field in chip-select pin assignment register 1 (CSPAR1). ECLK
operation during low-power stop is described in the following paragraph. Refer to 5.9
Chip-Selects for more information about the external bus clock.
Low-power operation is initiated by the CPU16. To reduce power consumption selec-
tively, the CPU can set the STOP bits in each module configuration register. To mini-
mize overall microcontroller power consumption, the CPU can execute the LPSTOP
instruction which causes the SCIM2 to turn off the system clock.
When individual module STOP bits are set, clock signals inside each module are
turned off, but module registers are still accessible.
When the CPU executes LPSTOP, a special CPU space bus cycle writes a copy of
the current interrupt mask into the clock control logic. The SCIM2 brings the MCU out
of low-power stop mode when one of the following exceptions occur:
Refer to 5.6.4.2 LPSTOP Broadcast Cycle for more information.
During a low-power stop mode, unless the system clock signal is supplied by an
external source and that source is removed, the SCIM clock control logic and the SCIM
clock signal (SCIMCLK) continue to operate. The periodic interrupt timer and input
logic for the RESET and IRQ pins are clocked by SCIMCLK. The SCIM2 can also
continue to generate the CLKOUT signal while in low-power stop mode.
During low-power stop mode, the address bus continues to drive the LPSTOP
instruction, and bus control signals are negated. I/O pins configured as outputs con-
tinue to hold their previous state; I/O pins configured as inputs will be in a three-state
condition.
STSCIM and STEXT bits in SYNCR determine clock operation during low power stop
mode.
The flow chart shown in Figure 5-6 summarizes the effects of the STSCIM and STEXT
bits when the MCU enters normal low-power stop mode. Any clock in the off state is
held low. If the synthesizer VCO is turned off during low-power stop mode, there is a
PLL relock delay after the VCO is turned back on.
• RESET
• Trace
• SCIM2 interrupt of higher priority than the stored interrupt mask
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MC68HC16Y3/916Y3
USER’S MANUAL