mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 438

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

D.7.16 Command RAM
CR[0:F] — Command RAM
CONT — Continue
BITSE — Bits per Transfer Enable
DT — Delay after Transfer
DSCK — PCS to SCK Delay
D-60
MOTOROLA
Command RAM is used by the QSPI when in master mode. The CPU16 writes one
byte of control information to this segment for each QSPI command to be executed.
The QSPI cannot modify information in command RAM.
Command RAM consists of 16 bytes. Each byte is divided into two fields. The periph-
eral chip-select field enables peripherals for transfer. The command control field pro-
vides transfer options.
A maximum of 16 commands can be in the queue. Queue execution proceeds from
the address in NEWQP through the address in ENDQP (both of these fields are in
SPCR2).
0 = Control of chip selects returned to PORTQS after transfer is complete.
1 = Peripheral chip selects remain asserted after transfer is complete. This allows
0 = Eight bits
1 = Number of bits set in BITS field of SPCR0.
0 = Delay after transfer is 17
1 = SPCR1 DTL[7:0] specifies delay after transfer.
0 = PCS valid to SCK delay is one-half SCK.
1 = SPCR1 DSCKL[6:0] specifies delay from PCS valid to SCK.
for transfers greater than 16 bits to peripherals without deassertion of their chip-
selects.
NOTES:
CONT
CONT
1. The PCS0 bit represents the dual-function PCS0/SS.
—
7
COMMAND CONTROL
BITSE
BITSE
—
Freescale Semiconductor, Inc.
6
For More Information On This Product,
DT
DT
—
5
Go to: www.freescale.com
f
DSCK
DSCK
sys
—
4
.
PCS3
PCS3
—
3
PERIPHERAL CHIP SELECT
PCS2
PCS2
—
2
PCS1
PCS1
—
1
$YFFD40 – $YFFD4F
MC68HC16Y3/916Y3
PCS0
PCS0
—
0
USER’S MANUAL
1
1