mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 274

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

SCK (CPOL = 0)
SCK (CPOL = 1)
12.3.4.2 CPHA = 1 Transfer Format
12-10
(FROM MASTER)
(FROM SLAVE)
SS (TO SLAVE)
MOTOROLA
MISO
When CPHA equals zero, the SS line must be negated and reasserted between each
successive serial byte. If the slave writes data to the SPI data register while SS is as-
serted (low), a write collision error results. To avoid this problem, the slave should read
bit three of PORTMCP, which indicates the state of the SS pin, before writing to the
SPDR again.
Figure 12-4 is a timing diagram of an eight-bit, MSB-first SPI transfer in which CPHA
equals one. Two waveforms are shown for SCK, one for CPOL equal to zero and
another for CPOL equal to one. The diagram may be interpreted as a master or slave
timing diagram since the SCK, MISO and MOSI pins are directly connected between
the master and the slave. The MISO signal shown is the output from the slave and the
MOSI signal shown is the output from the master. The SS line is the slave select input
to the slave.
For a master, writing to the SPDR initiates the transfer. For a slave, the first edge of
SCK indicates the start of a transfer. The SPI is left-shifted on the first and each
succeeding odd clock edge, and data is latched on the second and succeeding even
clock edges.
MOSI
(FOR REFERENCE)
SCK CYCLE #
* NOT DEFINED BUT NORMALLY LSB OF PREVIOUSLY TRANSMITTED CHARACTER
*
Figure 12-4 CPHA = 1 SPI Transfer Format
MULTICHANNEL COMMUNICATION INTERFACE
Freescale Semiconductor, Inc.
MSB
MSB
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For More Information On This Product,
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Go to: www.freescale.com
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MC68HC16Y3/916Y3
LSB
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USER’S MANUAL
LSB
CPHA = 1 SPI TRANSFER