mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 277

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

12.4 Serial Communication Interface (SCI)
12.4.1 SCI Registers
MC68HC16Y3/916Y3
USER’S MANUAL
After correcting the problems that led to the mode fault, clear MODF by reading the
SPSR while MODF is set and then writing to the SPCR. Control bits SPE and MSTR
may be restored to their original set state during this clearing sequence or after the
MODF bit has been cleared. Hardware does not allow the user to set the SPE and
MSTR bits while MODF is a logic one except during the proper clearing sequence.
The SCI submodule contains two independent SCI systems. Each is a full-duplex
universal asynchronous receiver transmitter (UART). This SCI system is fully
compatible with SCI systems found on other Motorola devices, such as the M68HC11
and M68HC05 families.
The SCI uses a standard non-return to zero (NRZ) transmission format. An on-chip
baud-rate generator derives standard baud-rate frequencies from the MCU oscillator.
Both the transmitter and the receiver are double buffered, so that back-to-back
characters can be handled easily even if the CPU is delayed in responding to the
completion of an individual character. The SCI transmitter and receiver are functionally
independent but use the same data format and baud rate.
Figure 12-5 shows a block diagram of the SCI transmitter. Figure 12-6 shows a block
diagram of the SCI receiver.
The two independent SCI systems are called SCIA and SCIB. These SCIs are
identical in register set and hardware configuration, providing an application with full
flexibility in using the dual SCI system. References to SCI registers in this section do
not always distinguish between the two SCI systems. A reference to SCCR1, for
example, applies to both SCCR1A (SCIA control register 1) and SCCR1B (SCIB
control register 1).
The SCI programming model includes the MCCI global and pin control registers and
eight SCI registers. Each of the two SCI units contains two SCI control registers, one
status register, and one data register. Refer to D.8.9 SCI Control Register 0, D.8.11
SCI Status Register, and D.8.12 SCI Data Register for register bit and field
definitions.
All registers may be read or written at any time by the CPU. Rewriting the same value
to any SCI register does not disrupt operation; however, writing a different value into
an SCI register when the SCI is running may disrupt operation. To change register
values, the receiver and transmitter should be disabled with the transmitter allowed to
finish first. The status flags in the SCSR may be cleared at any time.
1. Forces the MSTR control bit to zero to reconfigure the SPI as a slave.
2. Forces the SPE control bit to zero to disable the SPI system.
3. Sets the MODF status flag and generates an SPI interrupt if SPIE = 1.
4. Clears the appropriate bits in the MDDR to configure all SPI pins except the SS
pin as inputs.
MULTICHANNEL COMMUNICATION INTERFACE
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
MOTOROLA
12-13