mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 125

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.4.3 Halt Monitor
5.4.4 Spurious Interrupt Monitor
5.4.5 Software Watchdog
MC68HC16Y3/916Y3
USER’S MANUAL
The monitor does not check DSACK response on the external bus unless the CPU16
initiates a bus cycle. The BME bit in SYPCR enables the internal bus monitor for
internal to external bus cycles. If a system contains external bus masters, an external
bus monitor must be implemented and the internal-to-external bus monitor option must
be disabled.
When monitoring transfers to an 8-bit port, the bus monitor does not reset until both
byte accesses of a word transfer are completed. Monitor timeout period must be at
least twice the number of clocks that a single byte access requires.
The halt monitor responds to an assertion of the HALT signal on the internal bus,
caused by a double bus fault. A flag in the reset status register (RSR) can indicate that
the last reset was caused by the halt monitor. Halt monitor reset can be inhibited by
the halt monitor (HME) enable bit in SYPCR. Refer to 5.6.5.2 Double Bus Faults for
more information.
During interrupt exception processing, the CPU16 normally acknowledges an interrupt
request, arbitrates among various sources of interrupt, recognizes the highest priority
source, and then acquires a vector or responds to a request for autovectoring. The
spurious interrupt monitor asserts the internal bus error signal (BERR) if no interrupt
arbitration occurs during interrupt exception processing. The assertion of BERR caus-
es the CPU16 to load the spurious interrupt exception vector into the program counter.
The spurious interrupt monitor cannot be disabled. Refer to 5.8 Interrupts for further
information. For detailed information about interrupt exception processing, refer to
4.13 Exceptions.
The software watchdog is controlled by the software watchdog enable (SWE) bit in
SYPCR. When enabled, the watchdog requires that a service sequence be written to
the software service register (SWSR) on a periodic basis. If servicing does not take
place, the watchdog times out and asserts the RESET signal.
Each time the service sequence is written, the software watchdog timer restarts. The
sequence to restart the software watchdog consists of the following steps:
• Write $55 to SWSR.
• Write $AA to SWSR.
Freescale Semiconductor, Inc.
BMT[1:0]
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Table 5-4 Bus Monitor Period
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Bus Monitor Timeout Period
64 System clocks
32 System clocks
16 System clocks
8 System clocks
MOTOROLA
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