mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 467

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mc68hc916y3

Manufacturer Part Number
mc68hc916y3
Description
Mc68hc16y3 16 Bit Microcontroller
Manufacturer
Freescale Semiconductor, Inc
Datasheet
T2CSL — TCR2 Counter Clock Edge
IARB[3:0] — Interrupt Arbitration ID
D.10.2 TPU2 Test Configuration Register
TCR — TPU2 Test Configuration Register
D.10.3 Development Support Control Register
DSCR — Development Support Control Register
HOT4 — Hang on T4
BLC — Branch Latch Control
CLKS — Stop Clocks (to TCRs)
MC68HC16Y3/916Y3
USER’S MANUAL
HOT4
15
0
RESET:
This bit and the T2CG control bit determine the clock source for TCR2. Refer to Table
14-6.
The IARB field is used to arbitrate between simultaneous interrupt requests of the
same priority. Each module that can generate interrupt requests must be assigned a
unique, non-zero IARB field value.
Used for factory test only.
0 = Exit wait on T4 state caused by assertion of HOT4.
1 = Enter wait on T4 state.
0 = Latch conditions into branch condition register before exiting halted state.
1 = Do not latch conditions into branch condition register before exiting the halted
0 = Do not stop TCRs.
1 = Stop TCRs during the halted state.
14
state or during the time-slot transition period.
13
The programmer should not change this value unless necessary
when developing custom TPU microcode.
NOT USED
12
T2CSL
Table 14-6 TCR2 Counter Clock Source
Freescale Semiconductor, Inc.
0
0
1
1
11
For More Information On This Product,
BLC
10
0
Go to: www.freescale.com
CLKS
9
0
T2CG
0
1
0
1
8
0
FRZ[1:0]
NOTE
7
0
Rise & fall transition T2CLK
Rise transition T2CLK
Fall transition T2CLK
Gated system clock
CCL
6
0
TCR2 Clock
BP
5
0
BC
4
0
BH
3
0
BL
2
0
$YFFE02
$YFFE04
MOTOROLA
BM
1
0
D-89
BT
0
0

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