mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 72

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

4.6.2 Extended Addressing Modes
4.6.3 Indexed Addressing Modes
4.6.4 Inherent Addressing Mode
4.6.5 Accumulator Offset Addressing Mode
4.6.6 Relative Addressing Modes
4.6.7 Post-Modified Index Addressing Mode
4-10
MOTOROLA
Regular extended mode instructions contain ADDR[15:0] in the word following the
opcode. The effective address is formed by concatenating the EK field and the 16-bit
byte address. EXT20 mode is used only by the JMP and JSR instructions. These
instructions contain a 20-bit effective address that is zero-extended to 24 bits to give
the instruction an even number of bytes.
In the indexed modes, registers IX, IY, and IZ, together with their associated extension
fields, are used to calculate the effective address.
For 8-bit indexed modes an 8-bit unsigned offset contained in the instruction is added
to the value contained in an index register and its extension field.
For 16-bit modes, a 16-bit signed offset contained in the instruction is added to the
value contained in an index register and its extension field.
For 20-bit modes, a 20-bit signed offset (zero-extended to 24 bits) is added to the val-
ue contained in an index register. These modes are used for JMP and JSR instructions
only.
Inherent mode instructions use information directly available to the processor to deter-
mine the effective address. Operands, if any, are system resources and are thus not
fetched from memory.
Accumulator offset modes form an effective address by sign-extending the content of
accumulator E to 20 bits, then adding the result to an index register and its associated
extension field. This mode allows use of an index register and an accumulator within
a loop without corrupting accumulator D.
Relative modes are used for branch and long branch instructions. If a branch condition
is satisfied, a byte or word signed two’s complement offset is added to the concatenat-
ed PK field and program counter. The new PK:PC value is the effective address.
Post-modified index mode is used by the MOVB and MOVW instructions. A signed 8-
bit offset is added to index register X after the effective address formed by XK : IX is
used.
• The PSHM and PULM instructions use an 8-bit immediate mask operand to
indicate which registers must be pushed to or pulled from the stack.
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MC68HC16Y3/916Y3
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