mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 166

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

5.8.4 Interrupt Processing Summary
5-58
MOTOROLA
Because the EBI manages external interrupt requests, the SCIM2 IARB value is used
for arbitration between internal and external interrupt requests. The reset value of
IARB for the SCIM2 is %1111, and the reset IARB value for all other modules is
%0000.
Although arbitration is intended to deal with simultaneous requests of the same
interrupt level, it always takes place, even when a single source is requesting service.
This is important for two reasons: the EBI does not transfer the interrupt acknowledge
read cycle to the external bus unless the SCIM2 wins contention, and failure to con-
tend causes the interrupt acknowledge bus cycle to be terminated early by a bus error.
When arbitration is complete, the module with both the highest asserted interrupt level
and the highest arbitration priority must terminate the bus cycle. Internal modules
place an interrupt vector number on the data bus and generate appropriate internal
cycle termination signals. In the case of an external interrupt request, after the interrupt
acknowledge cycle is transferred to the external bus, the appropriate external device
must respond with a vector number, then generate data size acknowledge (DSACK)
termination signals. If the device does not respond in time, the SCIM2 bus monitor, if
enabled, asserts the bus error signal (BERR), and a spurious interrupt exception is
taken.
Chip-select logic can also be used to generate internal DSACK signals in response to
interrupt acknowledgement cycles. Refer to 5.9.3 Using Chip-Select Signals for Inter-
rupt Acknowledge for more information. Chip-select address match logic functions
only after the EBI transfers an interrupt acknowledge cycle to the external bus follow-
ing IARB contention. All interrupts from internal modules have their associated IACK
cycles terminated with an internal DSACK. Thus, user vectors (instead of autovectors)
must always be used for interrupts generated from internal modules. If an internal
module makes an interrupt request of a certain priority, and the appropriate chip-select
registers are programmed to generate DSACK signals in response to an interrupt ac-
knowledge cycle for that priority level, chip-select logic does not respond to the inter-
rupt acknowledge cycle, and the internal module supplies a vector number and
generates internal cycle termination signals.
For periodic timer interrupts, the PIRQ[2:0] field in the periodic interrupt control register
(PICR) determines PIT priority level. A PIRQ[2:0] value of %000 means that PIT
interrupts are inactive. By hardware convention, when the CPU16 receives simulta-
neous interrupt requests of the same level from more than one SCIM2 source (includ-
ing external devices), the periodic interrupt timer is given the highest priority, followed
by the IRQ pins.
A summary of the entire interrupt processing sequence follows. When the sequence
begins, a valid interrupt service request has been detected and is pending.
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MC68HC16Y3/916Y3
USER’S MANUAL