mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 477

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

STOP — Stop Mode Control
FRZ — Freeze Mode Control
BOOT — Boot Control
LOCK — Lock Registers
MC68HC16Y3/916Y3
USER’S MANUAL
STOP can be set either by pulling data bus pin DATA12 low during reset or by the cor-
responding shadow bit. The TPUFLASH array is inaccessible during low-power stop.
The array can be re-enabled by clearing STOP. If STOP is set during programming or
erasing, the program/erase voltage is automatically turned off. However, the enable
program/erase bit (ENPE) remains set. If STOP is cleared, program/erase voltage is
automatically turned back on unless ENPE is cleared. To achieve a true low-power
stop when the TPUFLASH is in TPU mode, stop both the TPUFLASH and the TPU2.
This has no effect on the TPU microcode store.
Even though IMB accesses are prevented if STOP is set, the STOP bit has no effect
on TPU2 accesses. A TPUFLASH with the STOP bit set can still provide microcode to
the TPU2.
In TPU mode, this bit has no effect since programming cannot be done in TPU Mode.
Entering FREEZE Mode when programming or erasing is in progress can put excess
stress on the TPU flash EEPROM array, as the program/erase voltage is not automat-
ically turned off when the internal FREEZE line is asserted and FRZ = 1.
On reset, BOOT takes on the value stored in its associated shadow bit. If BOOT = 0
and STOP = 0, the module responds to program space accesses of IMB addresses
$000000 to $000006 following reset, and the contents of TFBS[3:0] are used as boot-
strap vectors. After address $000006 is read, the module responds normally to control
block or array addresses only. If the TPU flash EEPROM is configured for boot mode
as well as to enter TPU mode automatically out of reset, the TPUFLASH performs the
bootstrap accesses first, then provides microcode to the TPU2.
0 = Normal operation.
1 = Low-power stop operation (provided the TPUFLASH in not in TPU mode). The
0 = Disable program/erase voltage while FREEZE is asserted.
1 = Allow ENPE bit to turn on the program/erase voltage while FREEZE is
0 = TPUFLASH responds to bootstrap vector addresses after reset.
1 = TPUFLASH does not respond to bootstrap vector addresses after reset.
0 = Write-locking disabled.
1 = Write-locked registers protected.
TPUFLASH is disabled from IMB accesses.
asserted.
Avoid using a base address value that causes the module's own ar-
ray to overlap any but its own control registers. If a portion of the ar-
ray overlaps its own register block, the registers remain accessible,
but accesses to that portion of the array are ignored. If the array over-
laps the control block of any other module, however, reads of the
overlapping registers become indeterminate.
Freescale Semiconductor, Inc.
For More Information On This Product,
Go to: www.freescale.com
NOTE
MOTOROLA
D-99