mc68hc916y3 Freescale Semiconductor, Inc, mc68hc916y3 Datasheet - Page 296

• Manufacturer Part Number: mc68hc916y3
• Description: Mc68hc16y3 16 Bit Microcontroller
• Manufacturer: Freescale Semiconductor, Inc

13.5.4 Pulse Accumulator Input Pin
13.5.5 Pulse-Width Modulation
13.5.6 Auxiliary Timer Clock Input
13.6 General-Purpose I/O
13-8
MOTOROLA
The pulse accumulator input (PAI) pin connects a discrete signal to the pulse accumu-
lator for timed or gated pulse accumulation. PAI has hysteresis. Any pulse longer than
two system clocks is guaranteed to be valid and any pulse shorter than one system
clock is ignored. It can be used as a general-purpose input pin. Refer to 13.10 Pulse
Accumulator for more information.
Pulse-width modulation (PWMA/B) pins carry pulse-width modulator outputs. The
modulators can be programmed to generate a periodic waveform of variable frequen-
cy and duty cycle. PWMA can be used to output the clock selected as the input to the
PWM counter. These pins can also be used for general-purpose output. Refer to 13.11
Pulse-Width Modulation Unit for more information.
The auxiliary timer clock input (PCLK) pin connects an external clock to the GPT. The
external clock can be used as the clock source for the capture/compare unit or the
PWM unit in place of one of the prescaler outputs. PCLK has hysteresis. Any pulse
longer than two system clocks is guaranteed to be valid and any pulse shorter than
one system clock is ignored. This pin can also be used as a general-purpose input pin.
Refer to 13.7 Prescaler for more information.
Any GPT pin can be used for general-purpose I/O when it is not used for another pur-
pose. Capture/compare pins are bidirectional, others can be used only for output or
input. I/O direction is controlled by a data direction bit in the port GP data direction reg-
ister (DDRGP).
Parallel data is read from and written to the port GP data register (PORTGP). Pin data
can be read even when pins are configured for a timer function. Data read from PORT-
GP always reflects the state of the external pin, while data written to PORTGP may
not always affect the external pin.
Data written to PORTGP does not immediately affect pins used for output compare
functions, but the data is latched. When an output compare function is disabled, the
last data written to PORTGP is driven out on the associated pin if it is configured as
an output. Data written to PORTGP can cause input captures if the corresponding pin
is configured for input capture function.
The pulse accumulator input (PAI) and the external clock input (PCLK) pins provide
general-purpose input. The state of these pins can be read by accessing the PAIS and
PCLKS bits in the pulse accumulator control register (PACTL).
Pulse-width modulation A and B (PWMA/B) output pins can serve as general-purpose
outputs. The force PWM value (FPWMx) and the force logic one (F1x) bits in the com-
pare force (CFORC) and PWM control (PWMC) registers, respectively, control their
operation.
Freescale Semiconductor, Inc.
For More Information On This Product,
GENERAL-PURPOSE TIMER
Go to: www.freescale.com
MC68HC16Y3/916Y3
USER’S MANUAL